Ran Manevich

According to our database1, Ran Manevich authored at least 9 papers between 2009 and 2016.

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Bibliography

2016
Design and dynamic management of hierarchical NoCs.
Microprocess. Microsystems, 2016

2014
Designing single-cycle long links in hierarchical NoCs.
Microprocess. Microsystems, 2014

2013
ViLoCoN - An ultra-lightweight lossless VLSI video codec.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Dynamic traffic distribution among hierarchy levels in hierarchical Networks-on-Chip (NoCs).
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Handling global traffic in future CMP NoCs.
Proceedings of the International Workshop on System Level Interconnect Prediction, 2012

2011
A Cost Effective Centralized Adaptive Routing for Networks-on-Chip.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Centralized Adaptive Routing for NoCs.
IEEE Comput. Archit. Lett., 2010

2009
Best of both worlds: A bus enhanced NoC (BENoC).
Proceedings of the Third International Symposium on Networks-on-Chips, 2009


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