Ramtin Zand

CoRR, 2024

HiRISE: High-Resolution Image Scaling for Edge ML via In-Sensor Compression and Selective ROI.

[BibT_eX]

[DOI]

Sepehr Tabrizchi

Mohamadreza Mohammadi

Shaahin Angizi

CoRR, 2024

AssemAI: Interpretable Image-Based Anomaly Detection for Manufacturing Pipelines.

[BibT_eX]

[DOI]

Revathy Venkataramanan

Ramy F. Harik

Amit P. Sheth

CoRR, 2024

Flex-TPU: A Flexible TPU with Runtime Reconfigurable Dataflow Architecture.

[BibT_eX]

[DOI]

CoRR, 2024

Multi-Objective Neural Architecture Search for In-Memory Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Towards Efficient Deployment of Hybrid SNNs on Neuromorphic and Edge AI Hardware.

[BibT_eX]

[DOI]

James Seekings

Mahsa Ardakani

Proceedings of the International Conference on Neuromorphic Systems, 2024

HiRISE: High-Resolution Image Scaling for Edge ML via In-Sensor Compression and Selective ROI.

[BibT_eX]

[DOI]

Sepehr Tabrizchi

Shaahin Angizi

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Lightator: An Optical Near-Sensor Accelerator with Compressive Acquisition Enabling Versatile Image Processing.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Work in Progress: Real-time Transformer Inference on Edge AI Accelerators.

[BibT_eX]

[DOI]

Heath Smith

Proceedings of the 29th IEEE Real-Time and Embedded Technology and Applications Symposium, 2023

Application of Machine Learning for Quality Risk Factor Analysis of Electronic Assemblies.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

A Novel Stochastic LSTM Model Inspired by Quantum Machine Learning.

[BibT_eX]

[DOI]

Joseph Lindsay

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Realtime Facial Expression Recognition: Neuromorphic Hardware vs. Edge AI Accelerators.

[BibT_eX]

[DOI]

Heath Smith

James Seekings

Proceedings of the International Conference on Machine Learning and Applications, 2023

Caveline Detection at the Edge for Autonomous Underwater Cave Exploration and Mapping.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Machine Learning and Applications, 2023

Facial Expression Recognition at the Edge: CPU vs GPU vs VPU vs TPU.

[BibT_eX]

[DOI]

Heath Smith

Lareb Khan

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Units.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

IMAC-Sim: : A Circuit-level Simulator For In-Memory Analog Computing Architectures.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

Static hand gesture recognition for American sign language using neuromorphic hardware.

[BibT_eX]

[DOI]

Neuromorph. Comput. Eng., December, 2022

APTPU: Approximate Computing Based Tensor Processing Unit.

[BibT_eX]

[DOI]

Jason Kamran Eshraghian

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Xbar-Partitioning: A Practical Way for Parasitics and Noise Tolerance in Analog IMC Circuits.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Reliability-Aware Deployment of DNNs on In-Memory Analog Computing Architectures.

[BibT_eX]

[DOI]

CoRR, 2022

A Python Framework for SPICE Circuit Simulation of In-Memory Analog Computing Circuits.

[BibT_eX]

[DOI]

CoRR, 2022

Static Hand Gesture Recognition for American Sign Language using Neuromorphic Hardware.

[BibT_eX]

[DOI]

Mohammedreza Mohammadi

CoRR, 2022

Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Energy-Efficient Deployment of Machine Learning Workloads on Neuromorphic Hardware.

[BibT_eX]

[DOI]

James Seekings

Proceedings of the 13th IEEE International Green and Sustainable Computing Conference, 2022

MRAM-based Analog Sigmoid Function for In-memory Computing.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021

Probabilistic Interpolation Recoder for Energy-Error-Product Efficient DBNs With p-Bit Devices.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2021

An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

An Adaptive Sampling and Edge Detection Approach for Encoding Static Images for Spiking Neural Networks.

[BibT_eX]

[DOI]

Junlin Ou

Proceedings of the 12th International Green and Sustainable Computing Workshops, 2021

2020

Hardware-Algorithm Co-Design of a Compressed Fuzzy Active Learning Method.

[BibT_eX]

[DOI]

Ehsan Jokar

Sajad Haghzad Klidbary

Hadis Abolfathi

Saeed Bagheri Shouraki

Arash Ahmadi

IEEE Trans. Circuits Syst., 2020

A Single-Cycle MLP Classifier Using Analog MRAM-based Neurons and Synapses.

[BibT_eX]

[DOI]

CoRR, 2020

SOT-MRAM based Sigmoidal Neuron for Neuromorphic Architectures.

[BibT_eX]

[DOI]

CoRR, 2020

Electrically-Tunable Stochasticity for Spin-based Neuromorphic Circuits: Self-Adjusting to Variation.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

TSV Extrusion Morphology Classification Using Deep Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Machine Learning and Applications, 2020

2019

MRAM-Enhanced Low Power Reconfigurable Fabric With Multi-Level Variation Tolerance.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Composable Probabilistic Inference Networks Using MRAM-based Stochastic Neurons.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2019

Self-Organized Sub-bank SHE-MRAM-based LLC: An energy-efficient and variation-immune read and write architecture.

[BibT_eX]

[DOI]

Integr., 2019

AQuRate: MRAM-based Stochastic Oscillator for Adaptive Quantization Rate Sampling of Sparse Signals.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Clockless Spin-based Look-Up Tables with Wide Read Margin.

[BibT_eX]

[DOI]

Soheil Salehi

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

HSC-FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018

A Parity-Preserving Reversible QCA Gate with Self-Checking Cascadable Resiliency.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2018

Survivability Modeling and Resource Planning for Self-Repairing Reconfigurable Device Fabrics.

[BibT_eX]

[DOI]

IEEE Trans. Cybern., 2018

Synthesis of normally-off boolean circuits: An evolutionary optimization approach utilizing spintronic devices.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networks.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

Low-Energy Deep Belief Networks Using Intrinsic Sigmoidal Spintronic-based Probabilistic Neurons.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Logic-Encrypted Synthesis for Energy-Harvesting-Powered Spintronic-Embedded Datapath Design.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017

Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for Spin Hall Effect MRAM Device.

[BibT_eX]

[DOI]

Mohan Krishna Gopi Krishna

IEEE Trans. Very Large Scale Integr. Syst., 2017

Voltage-Based Concatenatable Full Adder Using Spin Hall Effect Switching.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Heterogeneous energy-sparing reconfigurable logic: spin-based storage and CNFET-based multiplexing.

[BibT_eX]

[DOI]