Ramiro Taco
Orcid: 0000-0003-3046-2364
According to our database1,
Ramiro Taco
authored at least 26 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
IEEE Trans. Very Large Scale Integr. Syst., December, 2024
Low Power, Energy Efficient and High Performance Triple Mode Logic for IoT Applications.
Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024
2023
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
Programmable All-in-One 4×8-/2×16-/1×32-Bits Dual Mode Logic Multiplier in 16 nm FinFET With Semi-Automatic Flow.
IEEE Access, 2023
Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
2022
A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic.
IEEE J. Solid State Circuits, 2022
DMTJ-Based Non-Volatile Ternary Content Addressable Memory for Energy-Efficient High-Performance Systems.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
2021
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI.
IEEE J. Solid State Circuits, 2019
Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits.
VLSI Design, 2015
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines.
Int. J. Circuit Theory Appl., 2015
2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014