Ramesh C. Tekumalla

According to our database, Ramesh C. Tekumalla authored at least 22 papers between 1996 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Innovative practices on memory test practice.

M. Casarsa, Gurgen Harutyunyan, Kaitlyn Chen, Ramesh Sharma, Giri Podichetty, Martin Keim, Sreejit Chakravarty, Ramesh C. Tekumalla

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

2015

Clock Domain Imbalances and Their Impact on Test Architecture.

Ramesh C. Tekumalla

Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

2014

Innovative practices session 1C: Existing/emerging low power techniques.

Charutosh Dixit, Ramesh C. Tekumalla, Wei Zhao, Nilanjan Mukherjee, Vivek Chickermane

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

On-chip Clock Testing and Frequency Measurement.

Ramesh C. Tekumalla, Prakash Krishnamoorthy

Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

Local Repair Signature Handling for Repairable Memories.

Ramesh C. Tekumalla, Prakash Krishnamoorthy

Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

On Handling Memory Scan Chains.

Surbhi Bansal, Aviansh Mendhalkar, Ramesh C. Tekumalla

Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

2013

Innovative practices session 2C: Memory test.

Charutosh Dixit, Ramesh C. Tekumalla, Sreejit Chakravarty, Manuel d'Abreu, Zhuoyu Bao, Concetta Riccobene

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Quotient prediction for low power division.

Prakash Krishnamoorthy, Ramesh C. Tekumalla

Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Power aware transformation of bandlimited signals.

Prakash Krishnamoorthy, Ramesh C. Tekumalla

Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

2006

An On-Chip Diagnosis Methodology for Embedded Cores with Replaceable Modules.

Ramesh C. Tekumalla

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2003

On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures.

Ramesh C. Tekumalla

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis.

Ramesh C. Tekumalla, Scott Davidson

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Identification of primitive faults in combinational and sequentialcircuits.

Ramesh C. Tekumalla, Premachandran R. Menon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

On Diagnosing Path Delay Faults in an At-Speed Environment.

Ramesh C. Tekumalla, Srikanth Venkataraman, Jayabrata Ghosh-Dastidar

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

2000

On Redundant Path Delay Faults in Synchronous Sequential Circuits.

Ramesh C. Tekumalla, Premachandran R. Menon

IEEE Trans. Computers, 2000

On Test Set Generation for Efficient Path Delay Fault Diagnosis.

Ramesh C. Tekumalla

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

1999

Robust testability of primitive faults using test points.

Ramesh C. Tekumalla, Premachandran R. Menon

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

On primitive fault test generation in non-scan sequential circuits.

Ramesh C. Tekumalla, Premachandran R. Menon

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

Delay Testing with Clock Control: An Alternative to Enhanced Scan.

Ramesh C. Tekumalla, Premachandran R. Menon

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan.

Ramesh C. Tekumalla, Premachandran R. Menon

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Test generation for primitive path delay faults in combinational circuits.

Ramesh C. Tekumalla, Premachandran R. Menon

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

Identifying Redundant Path Delay Faults in Sequential Circuits.

Ramesh C. Tekumalla, Premachandran R. Menon

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996