Ramesh Arvapalli
According to our database1,
Ramesh Arvapalli
authored at least 2 papers
between 2012 and 2013.
Collaborative distances:
Collaborative distances:
Timeline
2012
2013
0
1
2
1
1
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2013
An Energy Efficient 32-nm 20-MB Shared On-Die L3 Cache for Intel® Xeon® Processor E5 Family.
IEEE J. Solid State Circuits, 2013
2012
An energy efficient 32nm 20 MB L3 cache for Intel<sup>®</sup> Xeon<sup>®</sup> processor E5 family.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012