Ramautar Sharma

According to our database, Ramautar Sharma authored at least 5 papers between 1984 and 1989.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1989

A 6.75 ns 16*16 bit multiplier in single-level-metal CMOS technology.

Ramautar Sharma, Alexander D. Lopez, John A. Michejda, Steven J. Hillenius, John M. Andrews, Arnold J. Studwell

IEEE J. Solid State Circuits, August, 1989

1987

An AND-OR Parallel Execution System for Logic Program Evaluation.

Nam Sung Woo, Ramautar Sharma

Proceedings of the International Conference on Parallel Processing, 1987

Area-time efficient arithmetic elements for VLSI systems.

Ramautar Sharma

Proceedings of the 8th IEEE Symposium on Computer Arithmetic, 1987

1985

Architecture Design of a High-Quality Speech Synthesizer Based on the Multipulse LPC Technique.

Ramautar Sharma

IEEE J. Sel. Areas Commun., 1985

1984

A technology independent MOS multiplier generator.

Kung-Chao Chu, Ramautar Sharma

Proceedings of the 21st Design Automation Conference, 1984