Ramasubramanian Natarajan

Orcid: 0000-0003-1828-0496

Affiliations:
  • National Institute of Technology Tiruchirappalli, India


According to our database1, Ramasubramanian Natarajan authored at least 42 papers between 1980 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
OTK-based PUF CRP obfuscation for IoT device authentication.
Microelectron. J., February, 2024

Improving the performance of authentication protocols using efficient modular multi exponential technique.
Multim. Tools Appl., January, 2024

An EEG-Based Computational Model for Decoding Emotional Intelligence, Personality, and Emotions.
IEEE Trans. Instrum. Meas., 2024

Logic locking emulator on FPGA: A conceptual view.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Secure key exchange protocol and storage of logic locking key.
Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

2023
Device-specific security challenges and solution in IoT edge computing: a review.
J. Supercomput., December, 2023

Applying machine learning to enhance the cache performance using reuse distance.
Evol. Intell., August, 2023

An EEG-based subject-independent emotion recognition model using a differential-evolution-based feature selection algorithm.
Knowl. Inf. Syst., January, 2023

Improved Symbiotic organisms search for path planning of unmanned combat aerial vehicles.
J. Ambient Intell. Humaniz. Comput., 2023

2022
Secure and Energy Efficient Design of Multi-Modular Exponential Techniques for Public-Key Cryptosystem.
J. Commun. Inf. Networks, September, 2022

EAPIOD: ECC based authentication protocol for insider attack protection in IoD scenario.
Secur. Priv., 2022

Enhanced and secured random number generation for eUASBP.
Int. J. Syst. Assur. Eng. Manag., 2022

Efficient hardware realization and high radix implementation of modular multi exponential techniques for public key cryptography.
Microelectron. J., 2022

<i>ERMAP</i>: ECC-based robust mutual authentication protocol for smart grid communication with AVISPA simulations.
Int. J. Ad Hoc Ubiquitous Comput., 2022

Random Number Generation for PKI Using Controlled Anderson PUF.
Proceedings of the IEEE International Conference on Public Key Infrastructure and its Applications, 2022

2021
Design Space Exploration for Reducing Cost of Hardware Trojan Detection and Isolation during Architectural Synthesis.
J. Circuits Syst. Comput., 2021

Improving the Lifetime of Phase Change Memory by Shadow Dynamic Random Access Memory.
Int. J. Serv. Sci. Manag. Eng. Technol., 2021

Energy-Efficient Modular Exponential Techniques for Public-Key Cryptography - Efficient Modular Exponential Techniques
Springer, ISBN: 978-3-030-74523-3, 2021

2020
Hybrid Evolutionary Design Space Exploration Algorithm With Defence Against Third Party IP Vulnerabilities.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Insider Attack Protection: Lightweight Password-Based Authentication Techniques Using ECC.
IEEE Syst. J., 2020

A Memetic Algorithm-Based Design Space Exploration for Datapath Resource Allocation During High-Level Synthesis.
J. Circuits Syst. Comput., 2020

Enhancing the Lifetime of a Phase Change Memory with Bit-Flip Reversal.
J. Circuits Syst. Comput., 2020

eUASBP: enhanced user authentication scheme based on bilinear pairing.
J. Ambient Intell. Humaniz. Comput., 2020

Securing AES Accelerator from Key-Leaking Trojans on FPGA.
Int. J. Embed. Real Time Commun. Syst., 2020

Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems.
IEEE Embed. Syst. Lett., 2020

2019
Resource Efficient Metering Scheme for Protecting SoC FPGA Device and IPs in IoT Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Design of an Intelligent Data Cache with Replacement Policy.
Int. J. Embed. Real Time Commun. Syst., 2019

Enhanced Authentication Using Hybrid PUF with FSM for Protecting IPs of SoC FPGAs.
J. Electron. Test., 2019

Lightweight signature scheme to protect intellectual properties of Internet of things applications in system on chip field-programmable gate arrays.
Turkish J. Electr. Eng. Comput. Sci., 2019

Hardware Signature Generation Using a Hybrid PUF and FSM Model for an SoC Architecture.
Period. Polytech. Electr. Eng. Comput. Sci., 2019

Group influence based improved firefly algorithm for Design Space Exploration of Datapath resource allocation.
Appl. Intell., 2019

2018
Analysis of large deviations behavior of multi-GPU memory access in deep learning.
J. Supercomput., 2018

Dynamic Estimation of Temporary Failure in SoC FPGAs for Heterogeneous Applications.
J. Univers. Comput. Sci., 2018

Improving Power & Latency Metrics for Hardware Trojan Detection During High Level Synthesis.
Proceedings of the 9th International Conference on Computing, 2018

2017
Design of RSA processor for concurrent cryptographic transformations.
Microelectron. J., 2017

Energy efficient modular exponentiation for public-key cryptography based on bit forwarding techniques.
Inf. Process. Lett., 2017

Bit Forwarding 3-Bits Technique for Efficient Modular Exponentiation.
Int. J. Inf. Secur. Priv., 2017

Evaluation of password encrypted key exchange authentication techniques: design approach perspective: evaluation of PAKE protocol.
Proceedings of the 1st International Conference on Internet of Things and Machine Learning, 2017

2016
Efficient modular exponential algorithms compatible with hardware implementation of public-key cryptography.
Secur. Commun. Networks, 2016

A Survey on Performance of On-Chip Cache for Multi-core Architectures.
Proceedings of the International Conference on Informatics and Analytics, 2016

2011
Performance of Cache Memory Subsystems for Multicore Architectures
CoRR, 2011

1980
Computer education technology (CET).
Proceedings of the ACM 1980 Annual Conference, 1980


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