Ram Sivaramakrishnan

According to our database, Ram Sivaramakrishnan authored at least 7 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Composition of Experts on the SN40L Reconfigurable Dataflow Unit.

Raghu Prabhakar, Ram Sivaramakrishnan, Darshan Gandhi, Yun Du, Mingran Wang, Xiangyu Song, Kejie Zhang, Tianren Gao, Angela Wang, Xiaoyan Li, Joshua Brot, Calvin Leung, Tuowen Zhao, Mark Gottscho, Zhengyu Chen, Kaizhao Liang, Swayambhoo Jain, Urmish Thakker, Kevin J. Brown, Kunle Olukotun

IEEE Micro, 2024

SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts.

Raghu Prabhakar, Ram Sivaramakrishnan, Darshan Gandhi, Yun Du, Mingran Wang, Xiangyu Song, Kejie Zhang, Tianren Gao, Angela Wang, Karen Li, Yongning Sheng, Joshua Brot, Denis Sokolov, Apurv Vivek, Calvin Leung, Arjun Sabnis, Jiayu Bai, Tuowen Zhao, Mark Gottscho, David Jackson, Mark Luttrell, Manish K. Shah, Edison Chen, Kaizhao Liang, Swayambhoo Jain, Urmish Thakker, Dawei Huang, Sumti Jairath, Kevin J. Brown, Kunle Olukotun

CoRR, 2024

SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts.

Raghu Prabhakar, Ram Sivaramakrishnan, Darshan Gandhi, Yun Du, Mingran Wang, Xiangyu Song, Kejie Zhang, Tianren Gao, Angela Wang, Xiaoyan Li, Yongning Sheng, Joshua Brot, Denis Sokolov, Apurv Vivek, Calvin Leung, Arjun Sabnis, Jiayu Bai, Tuowen Zhao, Mark Gottscho, David Jackson, Mark Luttrell, Manish K. Shah, Zhengyu Chen, Kaizhao Liang, Swayambhoo Jain, Urmish Thakker, Dawei Huang, Sumti Jairath, Kevin J. Brown, Kunle Olukotun

Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

2015

M7: Oracle's Next-Generation Sparc Processor.

Kathirgamar Aingaran, Sumti Jairath, Georgios K. Konstadinidis, Serena Leung, Paul Loewenstein, Curtis McAllister, Stephen Phillips, Zoran Radovic, Ram Sivaramakrishnan, David Smentek, Thomas Wicki

IEEE Micro, 2015

2014

Next generation SPARC processor cache hierarchy.

Ram Sivaramakrishnan, Sumti Jairath

Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

2013

The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets.

John R. Feehrer, Sumti Jairath, Paul Loewenstein, Ram Sivaramakrishnan, David Smentek, Sebastian Turullols, Ali Vahidsafa

IEEE Micro, 2013

2012

SPARC T5: 16-core CMT processor with glueless 1-hop scaling to 8-sockets.

Sebastian Turullols, Ram Sivaramakrishnan

Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012