Ralph Mason

According to our database, Ralph Mason authored at least 35 papers between 1992 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

A 224 Gb/s 3 pJ/bit 40 dB Insertion Loss Transceiver in 3-nm FinFET CMOS.

Dirk Pfaff, Muhammad Nummer, Noman Hai, Jingjing Xia, Kai Ge Yang, Mohammad-Mahdi Mohsenpour, Choon-Haw C. H. Leong, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson R. Dick, Alif Zaman, Haitao Mei, Tahseen Shakir, Carlos Carvalho, Howard Huang, Pratibha Kumari, Ralph Mason, Fahmida Brishty, Ifrah Jaffri, David A. Yokoyama-Martin

IEEE J. Solid State Circuits, January, 2025

2024

7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS.

Dirk Pfaff, Muhammad Nummer, Noman Hai, Peter Xia, Kai Ge Yang, Mohammad-Mahdi Mohsenpour, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson R. Dick, Alif Zaman, Haitao Mei, Shahab Moazzeni, Tahseen Shakir, Carlos Carvalho, Howard Huang, Pratibha Kumari, Ralph Mason, Fahmida Brishty, Ifrah Jaffri

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2020

A sub-harmonic injection locking clock multiplier with FLL PVT calibrator.

Nahla T. Abou-El-Kheir, Ralph D. Mason, Mingze Li, Mustapha C. E. Yagoub

Microelectron. J., 2020

A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS.

Dirk Pfaff, Robert Abbott, Xin-Jie Wang, Shahaboddin Moazzeni, Ralph Mason, Raleigh Smith

IEEE J. Solid State Circuits, 2020

2019

A High-Performance Low Complexity All-Digital Fractional Clock Multiplier.

Nahla T. Abou-El-Kheir, Ralph D. Mason, Mingze Li, Mustapha C. E. Yagoub

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018

A 65 nm Compact High Performance Fully Synthesizable Clock Multiplier Based on an Injection Locked Ring Oscillator.

Nahla T. Abou-El-Kheir, Ralph D. Mason, Mingze Li, Mustapha C. E. Yagoub

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2015

Low-Phase Noise Clock Distribution Network Using Rotary Traveling-Wave Oscillators and Built-In Self-Test Phase Tuning Technique.

Zhanjun Bai, Xing Zhou, Ralph D. Mason, Gord Allan

IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014

A novel Injection Locked Rotary Traveling Wave Oscillator.

Zhanjun Bai, Xing Zhou, Ralph Mason

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

A 14b threshold configurable dynamically latched comparator for SAR ADCs.

Tony Forzley, Ralph Mason

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

2012

Complete SOC Transceiver in 0.18 µm CMOS Using Q-Enhanced Filtering, Sub-Sampling and Injection Locking.

Ralph D. Mason, Justin Fortier, Christopher A. DeVries

IEEE J. Solid State Circuits, 2012

Phase calibration techniques for injection-locking LO-path based phase-shifting phased-array architectures.

Yasser Soliman, Ralph Mason

Proceedings of the 2012 IEEE Radio and Wireless Symposium, 2012

2011

Complete SOC transceiver in 0.18µm CMOS using Q-enhanced filtering, sub-sampling and injection locking.

Ralph Mason, Justin Fortier, Chris DeVries

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2008

Subsampling Architecture for Low Power Receivers.

Christopher A. DeVries, Ralph D. Mason

IEEE Trans. Circuits Syst. II Express Briefs, 2008

A 14-mW 2.4-GHz CMOS transceiver for short range wireless sensor applications.

Reza Yousefi, Ralph Mason

Proceedings of the ESSCIRC 2008, 2008

2006

Quantization noise reduction using multiphase PLLs.

Igor Miletic, Ralph Mason

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Bandwidth Expansion in Sigma-Delta PLLs Using Multiphase VCOs.

Igor Miletic, Ralph Mason

Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2004

An RF sub-sampling mixer, PGA and Sigma Delta ADC for conversion at 900 MHz.

Ralph Mason, Chris DeVries, Eugene Ivanov

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A 0.18 μm CMOS 900 MHz receiver front-end using RF Q-enhanced filters.

Chris DeVries, Ralph Mason

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Improving the acquisition time of a PLL-based, integer-N frequency synthesizer.

Syed Irfan Ahmed, Ralph D. Mason

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

A dual edge-triggered phase-frequency detector architecture.

Syed Irfan Ahmed, Ralph D. Mason

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

RF, Q-enhanced bandpass filters in standard 0.18µm CMOS with direct digital tuning.

H. Ahmed, Chris DeVries, Ralph Mason

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A digitally tuned 1.1 GHz subharmonic injection-locked VCO in 0.18μm CMOS.

Hesham Ahmed, Christopher A. DeVries, Ralph Mason

Proceedings of the ESSCIRC 2003, 2003

2002

A 0.18μm CMOS, high Q-enhanced bandpass filter with direct digital tuning.

Chris DeVries, Ralph Mason

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001

A differential bipolar quasi-passive cyclic digital-to-analog converter with 4.416 MSps conversion rate and -77 dB THD.

Mohsen Moussavi, Ralph Mason, Calvin Plett

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

1999

Phase Measurements for Direct Conversion AM Radio Navigation.

Anh Dinh, Ralph Mason, Ron Palmer, Ken Runtz

J. Intell. Transp. Syst., 1999

Mixed Signal DFT at GHz Frequencies.

Ralph Mason, Shing Ma

J. Electron. Test., 1999

Analog DFT Using an Undersampling Technique.

Ralph Mason, Shing Ma

IEEE Des. Test Comput., 1999

A toolset for construction of hybrid intelligent forecasting systems: application for water demand prediction.

Narate Lertpalangsunti, Christine W. Chan, Ralph Mason, Paitoon Tontiwachwuthikul

Artif. Intell. Eng., 1999

A VLSI Programmable Cellular Automata Array for Multiplication in GF (2ⁿ).

Chang N. Zhang, Ming Y. Deng, Ralph Mason

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

6.5 mW CMOS low noise amplifier at 1.9 GHz.

Shijun Yang, Ralph Mason, Calvin Plett

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

High speed V.32 trellis encoder/decoder implementation using FPGA.

Anh Dinh, Ralph Mason, Joe Toth

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Minimizing the effect of the host bus on the performance of a computational RAM logic-in-memory parallel-processing system.

Peter M. Nyasulu, Ralph Mason, W. Martin Snelgrove, Duncan G. Elliott

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998

Two Improved Algorithms and Hardware Implementations for Key Distribution Using Extended Programmable Cellular Automata.

Chang N. Zhang, Ming Y. Deng, Ralph Mason

Proceedings of the 14th Annual Computer Security Applications Conference (ACSAC 1998), 1998

1995

Mapping hierarchical neural networks to VLSI hardware.

Ralph D. Mason, William Robertson

Neural Networks, 1995

1992

An hierarchical VLSI neural network architecture.

Ralph Mason, William Robertson, Douglas Pincock

IEEE J. Solid State Circuits, January, 1992