Ralph K. Cavin III

According to our database, Ralph K. Cavin III authored at least 52 papers between 1977 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Nurturing the Growth of a National Infrastructure in Emerging Technologies.

Rafic Z. Makki, Victor V. Zhirnov, Ralph K. Cavin III, Sami Issa, Marco Iansiti

Proc. IEEE, 2018

2012

Science and Engineering Beyond Moore's Law.

Ralph K. Cavin III, Paolo Lugli, Victor V. Zhirnov

Proc. IEEE, 2012

Prolog to the Section on Science and Engineering Beyond Moore's Law.

Ralph K. Cavin III, Paolo Lugli, Victor V. Zhirnov

Proc. IEEE, 2012

2010

Memory Devices: Energy-Space-Time Tradeoffs.

Victor V. Zhirnov, Ralph K. Cavin III, Stephan Menzel, Eike Linn, Sebastian Schmelzer, Dennis Bräuhaus, Christina Schindler, Rainer Waser

Proc. IEEE, 2010

Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps.

Michel Brillouët, George Bourianoff, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida

Proc. IEEE, 2010

Nanoelectronics Research for Beyond CMOS Information Processing.

George Bourianoff, Michel Brillouët, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida

Proc. IEEE, 2010

Device and Architecture Outlook for Beyond CMOS Switches.

Kerry Bernstein, Ralph K. Cavin III, Wolfgang Porod, Alan C. Seabaugh, Jeff Welser

Proc. IEEE, 2010

2009

Scaling beyond CMOS: Turing-Heisenberg Rapproachment.

Victor V. Zhirnov, Ralph K. Cavin III

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008

An Assessment of Integrated Digital Cellular Automata Architectures.

Victor V. Zhirnov, Ralph K. Cavin III, Greg Leeming, Kosmas Galatsis

Computer, 2008

Emerging Nanoscale Memory and Logic Devices: A Critical Assessment.

James A. Hutchby, Ralph K. Cavin III, Victor V. Zhirnov, Joe E. Brewer, George Bourianoff

Computer, 2008

Emerging Research Architectures.

Ralph K. Cavin III, James A. Hutchby, Victor V. Zhirnov, Joe E. Brewer, George Bourianoff

Computer, 2008

Boolean Logic and Alternative Information-Processing Devices.

George Bourianoff, Joe E. Brewer, Ralph K. Cavin III, James A. Hutchby, Victor V. Zhirnov

Computer, 2008

The Viability of Cellular Automata Architectures for General Purpose Computing.

Victor V. Zhirnov, Greg Leeming, Kosmas Galatsis, Ralph K. Cavin III

Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

2006

A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling.

Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards

IEEE J. Solid State Circuits, 2006

2005

Future devices for information processing.

Ralph K. Cavin III, Victor V. Zhirnov

Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004

A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability.

Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards

IEEE Trans. Very Large Scale Integr. Syst., 2004

2003

Current-mode signaling in deep submicrometer global interconnects.

Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III

IEEE Trans. Very Large Scale Integr. Syst., 2003

A semiconductor industry perspective on future directions in ECE education.

Ralph K. Cavin III, William H. Joyner Jr., Virginia C. Wiggins

IEEE Trans. Educ., 2003

Limits to binary logic switch scaling - a gedanken model.

Victor V. Zhirnov, Ralph K. Cavin III, James A. Hutchby, George Bourianoff

Proc. IEEE, 2003

Accurate delay model and experimental verification for current/voltage mode on-chip interconnects.

Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Low-power design methodology for an on-chip bus with adaptive bandwidth capability.

Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III

Proceedings of the 40th Design Automation Conference, 2003

2002

Delay and power model for current-mode signaling in deep submicron global interconnects.

Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2000

Integrated parametric timing optimization of digital systems.

Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1997

Clocking Optimization and Distribution in Digital Systems with Scheduled Skews.

Hong-Yean Hsieh, Wentai Liu, Paul D. Franzon, Ralph K. Cavin III

J. VLSI Signal Process., 1997

The delay vernier pattern generation technique.

Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III

IEEE J. Solid State Circuits, 1997

A CMOS high-speed data recovery circuit using the matched delay sampling technique.

Jin-Ku Kang, Wentai Liu, Ralph K. Cavin III

IEEE J. Solid State Circuits, 1997

1995

High Speed, Fine Resolution Pattern Generation Using the Matched Delay Technique.

Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Concurrent timing optimization of latch-based digital systems.

Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

A technique for high-speed, fine-resolution pattern generation and its CMOS implementation.

Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III

Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994

A 250-MHz wave pipelined adder in 2-μm CMOS.

Wentai Liu, C. Thomas Gray, David Fan, William J. Farlow, Thomas A. Hughes, Ralph K. Cavin III

IEEE J. Solid State Circuits, September, 1994

A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution.

C. Thomas Gray, Wentai Liu, Wilhelmus A. M. Van Noije, Thomas A. Hughes, Ralph K. Cavin III

IEEE J. Solid State Circuits, March, 1994

Timing constraints for wave-pipelined systems.

C. Thomas Gray, Wentai Liu, Ralph K. Cavin III

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Circuit delay calculation considering data dependent delays.

C. Thomas Gray, Wentai Liu, Ralph K. Cavin III, Hong-Yean Hsieh

Integr., 1994

1993

A bit-serial VLSI architecture for generating moments in real-time.

Wentai Liu, Su-Shing Chen, Ralph K. Cavin III

IEEE Trans. Syst. Man Cybern., 1993

1991

Theoretical and Practical Issues in CMOS Wave Pipelining.

C. Thomas Gray, Thomas A. Hughes, Sanjay Arora, Wentai Liu, Ralph K. Cavin III

Proceedings of the VLSI 91, 1991

1990

Design of integrated circuits: directions and challenges.

Ralph K. Cavin III, Jeffrey L. Hilbert

Proc. IEEE, 1990

P³A: a partitionable parallel/pipeline architecture for real-time image processing.

C. Thomas Gray, Wentai Liu, Thomas A. Hughes, Ralph K. Cavin III, Su-Shing Chen

Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

The design of a high-performance scalable architecture for image processing applications.

C. Thomas Gray, Wentai Liu, Thomas A. Hughes, Ralph K. Cavin III

Proceedings of the Application Specific Array Processors, 1990

1989

Hamiltonian Cycles in the Shuffle-Exchange Network.

Wentai Liu, Thomas H. Hildebrandt, Ralph K. Cavin III

IEEE Trans. Computers, 1989

The Semiconductor Research Corporation: Cooperative research.

Ralph K. Cavin III, Larry W. Sumney, Robert M. Burger

Proc. IEEE, 1989

1988

Rasterization theory, architectures, and implementations for a class of two-dimensional problems.

Wentai Liu, Ralph K. Cavin III

Integr., 1988

Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions.

Wentai Liu, Tong-Fei Yeh, William E. Batchelor, Ralph K. Cavin III

Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

Bit-level concurrency in real-time geometric feature extractions.

Wentai Liu, Tong-Fei Yeh, William E. Batchelor, Ralph K. Cavin III

Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 1988

1986

A perspective on CMOS technology trends.

William C. Holton, Ralph K. Cavin III

Proc. IEEE, 1986

1984

The Impact of ICs on Computer Technology.

Robert M. Burger, Ralph K. Cavin III, William C. Holton, Larry W. Sumney

Computer, 1984

Introduction to the SRC design sciences program.

Ralph K. Cavin III

Proceedings of the 21st Design Automation Conference, 1984

1983

Microelectronic architectures and devices for signal and symbol processing.

Ralph K. Cavin III, Noel R. Strader

Integr., 1983

1982

Analysis of error-gradient adaptive linear estimators for a class of stationary dependent processes.

Stephen K. Jones, Ralph K. Cavin III, William M. Reed

IEEE Trans. Inf. Theory, 1982

1980

An Efficient Computational Procedure for the Evaluation of the M/M/I Transient State Occupancy Probabilities.

Stephen K. Jones, Ralph K. Cavin III, Donald A. Johnston

IEEE Trans. Commun., 1980

1977

On the Maximum Average Throughput Rate for a Tandem Node Network.

Stephen K. Jones, Ralph K. Cavin III, J. N. Holyoak

IEEE Trans. Commun., 1977

Dynamic Modeling and Control of Digital Communication Networks.

Stephen K. Jones, Ralph K. Cavin III

Computer, 1977

Distributed parameter system optimum control design via finite element discretization.

Ralph K. Cavin III, S. C. Tandon

Autom., 1977