Ralph Gerard B. Sangalang

According to our database, Ralph Gerard B. Sangalang authored at least 20 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 13.73 ns Input Time Range TDA Design Based on Adjustable Current Sources Using 40-nm CMOS Process.

Chua-Chin Wang, Oliver Lexter July A. Jose, Li Lin, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Anela L. Salvador

Circuits Syst. Signal Process., June, 2024

A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array.

Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Chua-Chin Wang

IEEE Trans. Very Large Scale Integr. Syst., May, 2024

A single-chip PFM-controlled LED driver with 0.5% illuminance variation.

Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Pang-Yen Lou, Chen-Cheng-Hung Hung, Pradyumna Vellanki, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tirso A. Ronquillo

Microelectron. J., 2024

Power Supply for Submerged Camera as Applied to Environmental Monitoring.

Mae Dyan E. Baynas, Anton Louise P. De Ocampo, Ralph Gerard B. Sangalang

Proceedings of the 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2024

Trends in Technological Areas using Patent Analytics: A Comparative Study on the Time Series Forecasting of International Patent Classification.

John Joshua F. Montañez, Ralph Gerard B. Sangalang

Proceedings of the 14th International Conference on System Engineering and Technology, 2024

A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process.

Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process.

Ralph Gerard B. Sangalang, Shiva Reddy, Lean Karlo S. Tolentino, You-Wei Shen, Oliver Lexter July A. Jose, Chua-Chin Wang

IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process.

Chua-Chin Wang, Lean Karlo S. Tolentino, Shao-Wei Lu, Oliver Lexter July A. Jose, Ralph Gerard B. Sangalang, Tzung-Je Lee, Pang-Yen Lou, Wei-Chih Chang

Integr., May, 2023

A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder.

Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee

Circuits Syst. Signal Process., April, 2023

A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process.

Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng, Yi-Jen Chiu, Yu-Cheng Lin, Oliver Lexter July A. Jose

IET Circuits Devices Syst., March, 2023

Developing an LTE Learning Material: Experiences from a University in a Developing Country.

Leinard C. Lontoc, Marjorie H. Basco, Vannesa Ann P. Sulit, Genesis Aubrey M. Magpantay, Mirasol C. Dilay, Ralph Gerard B. Sangalang

Proceedings of the International Conference on Information Technology, 2023

FPGA-Based Radio Transceiver Using the TV White Space for Disaster Response Operation.

Khryzz Lyden G. Cueto, Ricky Mae V. Santos, Claudette Jane C. Hilario, John Carl V. Aggari, Ralph Gerard B. Sangalang

Proceedings of the International Conference on Information Technology, 2023

A High Resolution And Wide Range Temperature Detector Using 180-nm CMOS Process.

Ralph Gerard B. Sangalang, Shih-Heng Luo, Chua-Chin Wang

Proceedings of the International Conference on IC Design and Technology, 2023

Passiveless Digitally Controlled Oscillator With Embedded PVT Detector Using 40-nm CMOS.

Ralph Gerard B. Sangalang, You-Wei Shen, Shiva Reddy, Lean Karlo S. Tolentino, Chua-Chin Wang

Proceedings of the 15th IEEE International Conference on ASIC, 2023

A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process.

Ralph Gerard B. Sangalang, Wei-Zhen Chen, Chua-Chin Wang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022

A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition.

Chua-Chin Wang, Ralph Gerard B. Sangalang, Chien-Ping Kuo, Hsin-Che Wu, Yi Hsu, Shen-Fu Hsiao, Chia-Hung Yeh

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process.

Shiva Reddy, Ralph Gerard B. Sangalang, Chua-Chin Wang

Proceedings of the International Conference on IC Design and Technology, 2022

A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture.

Ralph Gerard B. Sangalang, Shih-Heng Luo, Hsin-Che Wu, Bao-Qi He, Shen-Fu Hsiao, Chua-Chin Wang, Chewnpu Jou, Harry Hsia, Douglas C.-H. Yu

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit.

Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng

IEEE Trans. Circuits Syst. II Express Briefs, 2021

An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS.

Chua-Chin Wang, Oliver Lexter July A. Jose, Po-Kai Su, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Jessica Velasco, Tzung-Je Lee

Microelectron. J., 2021