Ralf Schmitt

According to our database1, Ralf Schmitt authored at least 6 papers between 2002 and 2012.

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Bibliography

2012
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.
IEEE J. Solid State Circuits, 2012

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.
IEEE J. Solid State Circuits, 2012

2011
On overcoming the limitations of single-ended signaling for graphics memory interfaces.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2008
Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
System Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor; Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2002
Implementation of a third-generation 1.1-GHz 64-bit microprocessor.
IEEE J. Solid State Circuits, 2002


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