Rakshith Saligram
Orcid: 0000-0002-7436-9375
According to our database1,
Rakshith Saligram
authored at least 12 papers
between 2013 and 2024.
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2024
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024
Cooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS Memories.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024
2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
2022
Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal Analyses.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
Proceedings of the VLSI-SoC: Design Trends, 2020
A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
2013
Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit.
CoRR, 2013
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Towards the design of fault tolerant reversible circuits components of ALU using new PCMF gate.
Proceedings of the International Conference on Advances in Computing, 2013