Rakshith Saligram

According to our database, Rakshith Saligram authored at least 12 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Cryogenic Operation of Computing-In-Memory based Spiking Neural Network.

Laith A. Shamieh, Wei-Chun Wang, Shida Zhang, Rakshith Saligram, Amol D. Gaidhane, Yu Cao, Arijit Raychowdhury, Suman Datta, Saibal Mukhopadhyay

Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024

Cooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS Memories.

Rakshith Saligram, Amol D. Gaidhane, Yu Kevin Cao, Suman Datta, Arijit Raychowdhury

Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024

2023

Cryogenic CMOS as an Enabler for Low Power Dynamic Logic.

Rakshith Saligram, Suman Datta, Arijit Raychowdhury

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

2022

Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal Analyses.

Rakshith Saligram, Suman Datta, Arijit Raychowdhury

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing.

Wriddhi Chakraborty, P. Shrestha, A. Gupta, Rakshith Saligram, Samuel Spetalnick, J. Campbell, Arijit Raychowdhury, Suman Datta

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance.

Rakshith Saligram, Divya Prasad, David Pietromonaco, Arijit Raychowdhury, Brian Cline

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications.

Rakshith Saligram, Suman Datta, Arijit Raychowdhury

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020

Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication.

Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury

Proceedings of the VLSI-SoC: Design Trends, 2020

A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration.

Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

2013

Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit.

Rakshith Saligram, Shrihari Shridhar Hegde, Shashidhar A. Kulkarni, H. R. Bhagyalakshmi, M. K. Venkatesha

CoRR, 2013

Design of Low Logical Cost Conservative Reversible Adders Using Novel PCTG.

Rakshith Saligram

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Towards the design of fault tolerant reversible circuits components of ALU using new PCMF gate.

Rakshith Saligram, T. R. Rakshith

Proceedings of the International Conference on Advances in Computing, 2013