Rakesh Malik

According to our database, Rakesh Malik authored at least 18 papers between 2007 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2018

Fast Analysis of Time Interval Error in Current-Mode Drivers.

Jai Narayan Tripathi, Ramachandra Achar, Rakesh Malik

IEEE Trans. Very Large Scale Integr. Syst., 2018

2017

A 0.065-mm² 19.8-mW Single-Channel Calibration-Free 12-b 600-MS/s ADC in 28-nm UTBB FD-SOI Using FBB.

Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh, Vivek Bhatia, Shivani Chaudhary, Vigyan Jain, Stéphane Le Tual, Rakesh Malik

IEEE J. Solid State Circuits, 2017

Distortion analysis for a DC-DC buck converter.

Vijender Kumar Sharma, Hitesh Shrimali, Jai Narayan Tripathi, Rakesh Malik

Proceedings of the International SoC Design Conference, 2017

Nonlinear modeling and analysis of buck converter using volterra series.

Hitesh Shrimali, Vijender Kumar Sharma, Jai Narayan Tripathi, Rakesh Malik

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016

A 0.065mm² 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB.

Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh, Vivek Bhatia, Shivani Chaudhary, Vigyan Jain, Stéphane Le Tual, Rakesh Malik

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

2015

Analysis of a serial link for power supply induced jitter.

Jai Narayan Tripathi, Hiten Advani, Raj Kumar Nagpal, Vijender Kumar Sharma, Rakesh Malik

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

2014

Decoupling network optimization in high speed systems by mixed-integer programming.

Jai Narayan Tripathi, Ashutosh Mahajan, Jayanta Mukherjee, Raj Kumar Nagpal, Rakesh Malik, Nitin Gupta

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Power Integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization.

Jai Narayan Tripathi, Raj Kumar Nagpal, Nitin Kumar Chhabra, Rakesh Malik, Jayanta Mukherjee, Prakash R. Apte

Proceedings of the International Symposium on Quality Electronic Design, 2013

Handwritten Musical Document Retrieval Using Music-Score Spotting.

Rakesh Malik, Partha Pratim Roy, Umapada Pal, Fumitaka Kimura

Proceedings of the 12th International Conference on Document Analysis and Recognition, 2013

2012

Selling to the BRIC: the background to the scholarly publishing market in India.

Rakesh Malik

Learn. Publ., 2012

Maintaining Power Integrity by damping the cavity-mode anti-resonances' peaks on a power plane by Particle Swarm Optimization.

Jai Narayan Tripathi, Raj Kumar Nagpal, Nitin Kumar Chhabra, Rakesh Malik, Jayanta Mukherjee

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Damping the cavity-mode anti-resonances' peaks on a power plane by swarm intelligence algorithms.

Jai Narayan Tripathi, Nitin Kumar Chhabra, Raj Kumar Nagpal, Rakesh Malik, Jayanta Mukherjee

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

Cost-effective optimization of serial link system for Signal Integrity and Power Integrity.

Raj Kumar Nagpal, Jai Narayan Tripathi, Rakesh Malik

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010

Robust optimization of serial link system for signal integrity and power integrity.

Jai Narayan Tripathi, Raj Kumar Nagpal, Rakesh Malik

Proceedings of the 1st IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2010

Modelling of Power Distribution Network and Decoupling Network Design for High Speed VLSI Design.

Abhishek Pathak, Sushanta K. Mandal, Raj Kumar Nagpal, Rakesh Malik

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

2009

Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links.

Raj Kumar Nagpal, Rakesh Malik, Jai Narayan Tripathi

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process.

Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process.

Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007