Rakesh Kumar Palani
Orcid: 0000-0003-4768-0560
According to our database1,
Rakesh Kumar Palani
authored at least 18 papers
between 2014 and 2024.
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Timeline
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Bibliography
2024
Analysis and Design of Low Noise Voltage Regulator With Integrated Single BJT Bandgap Reference Upto 10 mA Loads.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2024
A Wide Range Constant Transconductance Circuit Based on Negative Feedback for Analog Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A Novel 22.7 ppm/<sup>0</sup>C Voltage mode Sub-Bandgap Reference with robust startup nature.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2015
A 220-MS/s 9-Bit 2X Time-Interleaved SAR ADC With a 133-fF Input Capacitance and a FOM of 37 fJ/conv in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
A throughput-agnostic 11.9-13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
An eight channel analog-FFT based 450MS/s hybrid filter bank ADC with improved SNDR for multi-band signals in 40nm CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
A 4.6mW, 22dBm IIP3 all MOSCAP based 34-314MHz tunable continuous time filter in 65nm.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014