Rakesh Kumar
Orcid: 0000-0001-6306-304XAffiliations:
- Norwegian University of Science and Technology (NTNU), Trondheim, Norway
- University of Edinburgh, UK (former)
According to our database1,
Rakesh Kumar
authored at least 29 papers
between 2012 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on orcid.org
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on folk.ntnu.no
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on dl.acm.org
On csauthors.net:
Bibliography
2024
Proceedings of the 2nd Workshop on SErverless Systems, Applications and MEthodologies, 2024
2023
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
2022
ACM Trans. Archit. Code Optim., 2022
Proceedings of the Eighth International Workshop on Serverless Computing, 2022
Proceedings of the 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2022
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022
2021
CoRR, 2021
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
2020
Proceedings of the HASP@MICRO 2020: Hardware and Architectural Support for Security and Privacy, 2020
Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
2017
HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
2016
Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment.
ACM Trans. Comput. Syst., 2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
Quantitative characterization of the software layer of a HW/SW co-designed processor.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016
2014
Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment.
ACM Trans. Archit. Code Optim., 2014
2013
Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013
Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment.
Proceedings of the 20th Annual International Conference on High Performance Computing, 2013
2012
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012