Rakesh Kumar

Orcid: 0000-0001-6306-304X

Affiliations:
  • Norwegian University of Science and Technology (NTNU), Trondheim, Norway
  • University of Edinburgh, UK (former)


According to our database1, Rakesh Kumar authored at least 29 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
CoFaaS: Automatic Transformation-based Consolidation of Serverless Functions.
Proceedings of the 2nd Workshop on SErverless Systems, Applications and MEthodologies, 2024

2023
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

A Storage-Effective BTB Organization for Servers.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022
Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order Cores.
ACM Trans. Archit. Code Optim., 2022

Freeway to Memory Level Parallelism in Slice-Out-of-Order Cores.
CoRR, 2022

Impact of microarchitectural state reuse on serverless functions.
Proceedings of the Eighth International Workshop on Serverless Computing, 2022

Mitigating Unnecessary Throttling in Linux CFS Bandwidth Control.
Proceedings of the 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2022

A Specialized BTB Organization for Servers.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021
A Variable Vector Length SIMD Architecture for HW/SW Co-designed Processors.
CoRR, 2021

BTB-X: A Storage-Effective BTB Organization.
IEEE Comput. Archit. Lett., 2021

Twig: Profile-Guided BTB Prefetching for Data Center Applications.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2020
Shooting Down the Server Front-End Bottleneck.
ACM Trans. Comput. Syst., 2020

Fetch-Directed Instruction Prefetching Revisited.
CoRR, 2020

Uncovering Hidden Instructions in Armv8-A Implementations.
Proceedings of the HASP@MICRO 2020: Hardware and Architectural Support for Security and Privacy, 2020

Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019
Freeway: Maximizing MLP for Slice-Out-of-Order Execution.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Blasting through the Front-End Bottleneck with Shotgun.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

Boomerang: A Metadata-Free Architecture for Control Flow Delivery.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016
Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment.
ACM Trans. Comput. Syst., 2016

C<sup>3</sup>D: Mitigating the NUMA bottleneck via coherent DRAM caches.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Quantitative characterization of the software layer of a HW/SW co-designed processor.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

2014
Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment.
ACM Trans. Archit. Code Optim., 2014

2013
Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

Vectorizing for Wider Vector Units in a HW/SW Co-designed Environment.
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013

Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment.
Proceedings of the 20th Annual International Conference on High Performance Computing, 2013

2012
Speculative dynamic vectorization for HW/SW co-designed processors.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012


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