Rakesh H. Patel

According to our database, Rakesh H. Patel authored at least 11 papers between 2002 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2009

Nonlinear behavior study in digital bang-bang PLL.

Albert Vareljian, Mohsen Moussavi, William Bereza, Walter Fergusson, Charles E. Berndt, Rakesh H. Patel

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

Session 21 - Leveraging the third Dimension.

Rakesh H. Patel, Michael Seningen

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A.

Walter Fergusson, Rakesh H. Patel, William Bereza

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations.

William Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel

Proceedings of the 43rd Design Automation Conference, 2006

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs.

Rakesh H. Patel, William Bereza

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

Design considerations for 2nd-order and 3rd-order bang-bang CDR loops.

Shoujun Wang, Haitao Mei, Mashkoor Baig, William Bereza, Tadeusz Kwasniewski, Rakesh H. Patel

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Multi-protocol embedded PCS IP in a FPGA-SOC.

Ramanand Venkata, Vinson Chan, Binh Ton, Chong Lee, Huy Ngo, Malik Kabani, Tam Nguyen, Arch Zaliznyak, Ning Xue, Steven Shen, Michael Zheng, Michael Lai, Steve Park, Lana Chan, Divya Vijayaraghavan, John Lam, Rakesh H. Patel

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A signal integrity-based link performance simulation platform.

Yuming Tao, William Bereza, Rakesh H. Patel, Sergey Y. Shumarayev, Tad A. Kwasniewski

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Nanometer design intricacies.

Rakesh H. Patel, Paul Billig

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

Power estimation and thermal budgeting methodology for FPGAs.

Henry Y. Lui, Chong H. Lee, Rakesh H. Patel

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2002

Interconnect enhancements for a high-speed PLD architecture.

Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002