Rakesh Chadha

According to our database, Rakesh Chadha authored at least 7 papers between 1987 and 1999.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1999

Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs.

Lun Ye, Foong-Charn Chang, Peter Feldmann, Rakesh Chadha, Nagaraj Ns, Frank Cano

Proceedings of the 1999 Design, 1999

1992

Switched-capacitor simulation models for full-chips verification.

Tom Chanak, Rakesh Chadha, Kishore Singhal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

M³-a multilevel mixed-mode mixed A/D simulator.

Rakesh Chadha, Chandramouli Visweswariah, Chin-Fu Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

1988

Extension of a transistor level digital timing simulator to include first order analog behavior.

Rakesh Chadha, Chin-Fu Chen

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

M³-a multilevel mixed-mode mixed D/A simulator.

Rakesh Chadha, Chin-Fu Chen

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Model Development and Verification for High Level Analog Blocks.

Chandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

WATOPT -- An Optimizer for Circuit Applications.

Rakesh Chadha, Kishore Singhal, Jirí Vlach, Ernst Christen, Milan Vlach

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987