Rajshekar Kalayappan

According to our database, Rajshekar Kalayappan authored at least 18 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

faRM-LTL: A Domain-Specific Architecture for Flexible and Accelerated Runtime Monitoring of LTL Properties.

Amrutha Benny, Sandeep Chandran, Rajshekar Kalayappan, Ramchandra Phawade, Piyush P. Kurur

Proceedings of the Runtime Verification - 24th International Conference, 2024

CASH: Criticality-Aware Split Hybrid L1 Data Cache.

Shruthi Karunakar, Meenakshi Atkade, Akash Poptani, Rajshekar Kalayappan, Sandeep Chandran

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

On Decomposing Complex Test Cases for Efficient Post-silicon Validation.

C. Harshitha, Sundarapalli Harikrishna, Peddakotla Rohith, Sandeep Chandran, Rajshekar Kalayappan

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Dynamic Ineffectuality-based Clustered Architectures.

Rajshekar Kalayappan, Sandeep Chandran

CoRR, 2023

SANNA: Secure Acceleration of Neural Network Applications.

Akash Poptani, Abhishek Mittal, Rishit Saiya, Rajshekar Kalayappan, Sandeep Chandran

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2021

A Formal Approach to Accountability in Heterogeneous Systems-on-Chip.

Rajshekar Kalayappan, Smruti R. Sarangi

IEEE Trans. Dependable Secur. Comput., 2021

A Survey of Cache Simulators.

Hadi Brais, Rajshekar Kalayappan, Preeti Ranjan Panda

ACM Comput. Surv., 2021

2020

ChunkedTejas: A Chunking-based Approach to Parallelizing a Trace-Driven Architectural Simulator.

Rajshekar Kalayappan, Avantika Chhabra, Smruti R. Sarangi

ACM Trans. Model. Comput. Simul., 2020

2018

Providing Accountability in Heterogeneous Systems-on-Chip.

Rajshekar Kalayappan, Smruti R. Sarangi

ACM Trans. Embed. Comput. Syst., 2018

2017

ParTejas: A Parallel Simulator for Multicore Processors.

Geetika Malhotra, Rajshekar Kalayappan, Seep Goel, Pooja Aggarwal, Abhishek Sagar, Smruti R. Sarangi

ACM Trans. Model. Comput. Simul., 2017

A hardware implementation of the MCAS synchronization primitive.

Srishty Patel, Rajshekar Kalayappan, Ishani Mahajan, Smruti R. Sarangi

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

FluidCheck: A Redundant Threading-Based Approach for Reliable Execution in Manycore Processors.

Rajshekar Kalayappan, Smruti R. Sarangi

ACM Trans. Archit. Code Optim., 2016

SecCheck: A Trustworthy System with Untrusted Components.

Rajshekar Kalayappan, Smruti R. Sarangi

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015

Tejas Simulator : Validation against Hardware.

Smruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel

CoRR, 2015

Tejas: A java based versatile micro-architectural simulator.

Smruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel, Eldhose Peter

Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

SecX: A Framework for Collecting Runtime Statistics for SoCs with Multiple Accelerators.

Rajshekar Kalayappan, Smruti R. Sarangi

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014

Surveillance using non-stealthy sensors: A new intruder model.

Amitabha Bagchi, Rajshekar Kalayappan, Surabhi Sankhla

Secur. Commun. Networks, 2014

2013

A survey of checker architectures.

Rajshekar Kalayappan, Smruti R. Sarangi

ACM Comput. Surv., 2013