Rajiv Jain

Tong Sun

CoRR, 2020

Generative-Discriminative Feature Representations for Open-Set Recognition.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

Text and Style Conditioned GAN for the Generation of Offline-Handwriting Lines.

[BibT_eX]

[DOI]

Proceedings of the 31st British Machine Vision Conference 2020, 2020

A Joint Model for Document Segmentation and Segment Labeling.

[BibT_eX]

[DOI]

Proceedings of the 58th Annual Meeting of the Association for Computational Linguistics, 2020

2019

Multimodal Document Image Classification.

[BibT_eX]

[DOI]

Curtis Wigington

Proceedings of the 2019 International Conference on Document Analysis and Recognition, 2019

2015

Searching Heterogeneous Document Image Collections.

[BibT_eX]

[DOI]

PhD thesis, 2015

Localized document image change detection.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Document Analysis and Recognition, 2015

Novel line verification for multiple instance focused retrieval in document collections.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Document Analysis and Recognition, 2015

2014

Combining Local Features for Offline Writer Identification.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Frontiers in Handwriting Recognition, 2014

Scalable ranked retrieval using document images.

[BibT_eX]

[DOI]

Douglas W. Oard

Proceedings of the Document Recognition and Retrieval XXI, 2014

2013

Writer Identification Using an Alphabet of Contour Gradient Descriptors.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Document Analysis and Recognition, 2013

VisualDiff: Document Image Verification and Change Detection.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Document Analysis and Recognition, 2013

2012

Logo Retrieval in Document Images.

[BibT_eX]

[DOI]

Proceedings of the 10th IAPR International Workshop on Document Analysis Systems, 2012

2011

Offline Writer Identification Using K-Adjacent Segments.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Document Analysis and Recognition, 2011

Real-Time Planning for Covering an Initially-Unknown Spatial Environment.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Fourth International Florida Artificial Intelligence Research Society Conference, 2011

2002

Composite Applications: Process Based Application Development.

[BibT_eX]

[DOI]

Anil K. Nori

Proceedings of the Technologies for E-Services, Third International Workshop, 2002

2001

Defining the Next Generation e-Business Platform: A Discussion of the Asers eBusiness Platform.

[BibT_eX]

[DOI]

Anil Nori

Chandar Venkatraman

IEEE Data Eng. Bull., 2001

1997

Interest Based Collaboration Framework.

[BibT_eX]

[DOI]

R. K. Aditham

Murali Srinivasan

Proceedings of the 6th Workshop on Enabling Technologies (WET-ICE '97), 1997

1996

Valid Transformations: A New Class of Loop Transformations for High-Level Synthesis and Pipelined Scheduling Applications.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 1996

Incorporating performance and testability constraints during binding in high-level synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995

Global scheduling with code-motions for high-level synthesis applications.

[BibT_eX]

[DOI]

Yaw Fann

IEEE Trans. Very Large Scale Integr. Syst., 1995

InSyn: integrated scheduling for DSP applications.

[BibT_eX]

[DOI]

Alok Sharma

IEEE Trans. Signal Process., 1995

PARAS: system-level concurrent partitioning and scheduling.

[BibT_eX]

[DOI]

Wing Hang Wong

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Test application time reduction for scan based sequential circuits.

[BibT_eX]

[DOI]

Hao Zheng

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

1994

Optimal and heuristic algorithms for solving the binding problem.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1994

Lower-bound performance estimation for the high-level synthesis scheduling problem.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Incorporating testability considerations in high-level synthesis.

[BibT_eX]

[DOI]

J. Electron. Test., 1994

BINET: An Algorithm for Solving the Binding Problem.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on VLSI Design, 1994

Estimating Performance Characteristics of Loop Transformations.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Valid Transformations: A New Class of Loop Transformations.

[BibT_eX]

[DOI]

Proceedings of the 1994 International Conference on Parallel Processing, 1994

[BibT_eX]

[DOI]

Alok Sharma

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

RECALS II: a new list scheduling algorithm.

[BibT_eX]

[DOI]

Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994

Behavioral Synthesis of Testable Designs.

[BibT_eX]

[DOI]

Proceedings of the Digest of Papers: FTCS/24, 1994

Global Scheduling for High-Level Synthesis Applications.

[BibT_eX]

[DOI]

Yaw Fann

Proceedings of the 31st Conference on Design Automation, 1994

1993

Estimating architectural resources and performance for high-level synthesis applications.

[BibT_eX]

[DOI]

Alok Sharma

IEEE Trans. Very Large Scale Integr. Syst., 1993

1992

Predicting system-level area and delay for pipelined and nonpipelined designs.

[BibT_eX]

[DOI]

Nohbyung Park

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Estimating Lower-Bound Performance of Schedules Using a Relaxation Technique.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Incorporating Testability Considerations in High-Level Systhesis.

[BibT_eX]

[DOI]

Proceedings of the Digest of Papers: FTCS-22, 1992

Optimal Allocation and Binding in High-Level Synthesis.

[BibT_eX]

[DOI]

Renato De Leone

Proceedings of the 29th Design Automation Conference, 1992

Representing Conditional Branches for High-Level Synthesis Applications.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1991

Empirical Evaluation of Some High-Level Synthesis Scheduling Heuristics.

[BibT_eX]

[DOI]

Proceedings of the 28th Design Automation Conference, 1991

1990

MOSP: Module Selection for Pipelined Designs with Multi-Cycle Operations.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989

Experience with ADAM Synthesis System.

[BibT_eX]

[DOI]

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

On Array Storage for Conflict-Free Memory Access for Parallel Processors.

[BibT_eX]

Meera Balakrishnan

Cauligi S. Raghavendra

Proceedings of the International Conference on Parallel Processing, 1988

The POTATO chip architecture: a study in tradeoffs for signal processing chip design.

[BibT_eX]

[DOI]

Cauligi S. Raghavendra

C. Y. Tseng

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Area-time model for synthesis of non-pipelined designs.

[BibT_eX]

[DOI]

Mitch J. Mlinar

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Module Selection for Pipelined Synthesis.

[BibT_eX]

[DOI]

Nohbyung Park

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

Predicting Area-Time Tradeoffs for Pipelined Design.

[BibT_eX]

[DOI]