Rajit Karmakar

According to our database, Rajit Karmakar authored at least 22 papers between 2014 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A Cellular Automata Guided Finite-State-Machine Watermarking Strategy for IP Protection of Sequential Circuits.

Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay

IEEE Trans. Emerg. Top. Comput., 2022

2021

Efficient Key-Gate Placement and Dynamic Scan Obfuscation Towards Robust Logic Encryption.

Rajit Karmakar, Harshit Kumar, Santanu Chattopadhyay

IEEE Trans. Emerg. Top. Comput., 2021

2020

A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits.

Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur

IEEE Trans. Circuits Syst. II Express Briefs, 2020

A cellular automata guided two level obfuscation of Finite-State-Machine for IP protection.

Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay

Integr., 2020

Hardware IP Protection Using Logic Encryption and Watermarking.

Rajit Karmakar, Santanu Chattopadhyay

Proceedings of the IEEE International Test Conference, 2020

On Securing Scan Obfuscation Strategies Against ScanSAT Attack.

Rajit Karmakar, Santanu Chattopadhyay

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

A Particle Swarm Optimization Guided Approximate Key Search Attack on Logic Locking in The Absence of Scan Access.

Rajit Karmakar, Santanu Chattopadhyay

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Improving Security of Logic Encryption in Presence of Design-for-Testability Infrastructure.

Rajit Karmakar, Santanu Chattopadhyay, Mrityunjoy Chakraborty

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Cellular Automata Guided Obfuscation Strategy For Finite-State-Machine Synthesis.

Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits.

Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur

CoRR, 2018

On Finding Suitable Key-Gate Locations In Logic Encryption.

Rajit Karmakar, Harshit Kumar, Santanu Chattopadhyay

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Temperature and data size trade-off in dictionary based test data compression.

Rajit Karmakar, Santanu Chattopadhyay

Integr., 2017

A New Logic Encryption Strategy Ensuring Key Interdependency.

Rajit Karmakar, N. Prasad, Santanu Chattopadhyay, Rohit Kapur, Indranil Sengupta

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Enhancing security of logic encryption using embedded key generation unit.

Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur

Proceedings of the International Test Conference in Asia, 2017

Runtime mitigation of illegal packet request attacks in Networks-on-Chip.

N. Prasad, Rajit Karmakar, Santanu Chattopadhyay, Indrajit Chakrabarti

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Optimization of the IEEE 1687 access network for hybrid access schedules.

Srinivasa Shashank Nuthakki, Rajit Karmakar, Santanu Chattopadhyay, Krishnendu Chakrabarty

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Thermal-Safe Schedule Generation for System-on-Chip Testing.

Rajit Karmakar, Santanu Chattopadhyay

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015

Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling.

Rajit Karmakar, Santanu Chattopadhyay

Integr., 2015

Testing of 3D-stacked ICs with hard- and soft-dies - a Particle Swarm Optimization based approach.

Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Thermal-Aware Test Data Compression Using Dictionary Based Coding.

Rajit Karmakar, Santanu Chattopadhyay

Proceedings of the 28th International Conference on VLSI Design, 2015

Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints.

Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Particle Swarm Optimization guided multi-frequency power-aware System-on-Chip test scheduling using window-based peak power model.

Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014