Rajesh Raina

According to our database, Rajesh Raina authored at least 24 papers between 1991 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

Achieving Zero-Defects for Automotive Applications.

Rajesh Raina

Proceedings of the 2008 IEEE International Test Conference, 2008

2006

What is DFM & DFY and Why Should I Care ?

Rajesh Raina

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Have we overcome the challenges associated with SoC and multi-core testing?

Rajesh Raina

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Is the concern for soft-error overblown?

Rajesh Raina

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

Skew measurements in clock distribution circuits using an analytic signal method.

Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2002

Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.

Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A Wavelet-Based Timing Parameter Extraction Method.

Mani Soma, Welela Haileselassie, Jessica Yan, Rajesh Raina

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

valuating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits.

John Gatej, Lee Song, Carol Pyron, Rajesh Raina, Tom Munns

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor .

Dawit Belete, Ashutosh Razdan, William Schwarz, Rajesh Raina, Christopher Hawkins, Jeff Morehead

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture.

Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Very Low Cost Testers: Opportunities and Challenges.

Jay Bedsole, Rajesh Raina, Al Crouch, Magdy S. Abadir

IEEE Des. Test Comput., 2001

A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals.

Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, David Halter, Rajesh Raina, Jim Nissen

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Testing clock distribution circuits using an analytic signal method.

Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor.

Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Jitter measurements of a PowerPC^TM microprocessor using an analytic signal method.

Takahiro J. Yamaguchi, Mani Soma, David Halter, Jim Nissen, Rajesh Raina, Masahiro Ishida, Toshifumi Watanabe

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

DFT advances in Motorola's Next-Generation 74xx PowerPC^TM microprocessor.

Rajesh Raina, Robert Bailey, Dawit Belete, Vikram Khosa, Robert F. Molyneaux, Javier Prado, Ashutosh Razdan

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999

DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor.

Carol Pyron, Mike Alexander, James Golab, George Joos, Bruce Long, Robert F. Molyneaux, Rajesh Raina, Nandu Tendolkar

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Design-for-test methodology for Motorola PowerPC microprocessors.

Magdy S. Abadir, Rajesh Raina

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches.

Rajesh Raina, Robert F. Molyneaux

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997

T4: Verification.

Rajesh Raina, Jacob A. Abraham, A. K. Pujari

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

How Seriously Do You Take Your Possible-Detect Faults?

Rajesh Raina, Charles Njinda, Robert F. Molyneaux

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Efficient Testing of Clock Regenerator Circuits in Scan Designs.

Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh

Proceedings of the 34st Conference on Design Automation, 1997

1996

Functional Verification Methodology for the PowerPC 604 Microprocessor.

James Monaco, David Holloway, Rajesh Raina

Proceedings of the 33st Conference on Design Automation, 1996

1991

Signature Analysis with Modified Linear Feedback Shift Registers (M-LFSRs).

Rajesh Raina, Peter N. Marinos

Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991