Rajesh Pendurkar

According to our database1, Rajesh Pendurkar authored at least 9 papers between 1996 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

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PhD thesis 
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Links

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Bibliography

2008
DFX of a 3<sup>rd</sup> Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor.
Proceedings of the 2008 IEEE International Test Conference, 2008

2004
Distributed Diagnosis of Interconnections in SoC and MCM Designs.
J. Electron. Test., 2004

2002
A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC<sup>TM</sup> Chip Multi-Processors.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
Switching activity generation with automated BIST synthesis forperformance testing of interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

2000
CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1999
Single-probe traversal optimization for testing of MCM substrate interconnections.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998
A distributed BIST technique for diagnosis of MCM interconnections.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Synthesis of BIST hardware for performance testing of MCM interconnections.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1996
Optimal single probe traversal algorithm for testing of MCM substrat.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996


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