Rajesh Mittal

According to our database, Rajesh Mittal authored at least 7 papers between 2010 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Towards Single Pin Scan for Extremely Low Pin Count Test.

Mudasir S. Kawoosa, Rajesh K. Mittal, Maheedhar Jalasuthram, Rubin A. Parekhji

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2014

Systematic approach for trim test time optimization: Case study on a multi-core RF SOC.

Rajesh Mittal, Mudasir Kawoosa, Rubin A. Parekhji

Proceedings of the 2014 International Test Conference, 2014

2013

Tutorial T10: Post - Silicon Validation, Debug and Diagnosis.

Prabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh Tamarapalli, Sharad Kumar, Rajesh Mittal

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Towards adaptive test of multi-core RF SoCs.

Rajesh Mittal, Lakshmanan Balasubramanian, Y. B. Chethan Kumar, V. R. Devanathan, Mudasir Kawoosa, Rubin A. Parekhji

Proceedings of the Design, Automation and Test in Europe, 2013

2011

Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation.

Prakash Narayanan, Rajesh Mittal, Sumanth Poddutur, Vivek Singhal, Puneet Sabbarwal

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management.

Rajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji

Proceedings of the 2011 IEEE International Test Conference, 2011

2010

Test time reduction using parallel RF test techniques.

Rajesh Mittal, Adesh Sontakke, Rubin A. Parekhji

Proceedings of the 28th IEEE VLSI Test Symposium, 2010