Rajesh Chandrasekhara Panicker

According to our database, Rajesh Chandrasekhara Panicker authored at least 7 papers between 2007 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation.

Yi Sheng Chong, Rakshith Harish, Rajesh Chandrasekhara Panicker, Vishnu P. Nambiar, Anh Tuan Do

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2013

Project-Based Learning in Embedded Systems Education Using an FPGA Platform.

Akash Kumar, Shakith Fernando, Rajesh Chandrasekhara Panicker

IEEE Trans. Educ., 2013

2012

Development of an FPGA-based real-time P300 speller.

Kanav Khurana, Pooja Gupta, Rajesh Chandrasekhara Panicker, Akash Kumar

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011

An Asynchronous P300 BCI With SSVEP-Based Control State Detection.

Rajesh Chandrasekhara Panicker, Sadasivan Puthusserypady, Ying Sun

IEEE Trans. Biomed. Eng., 2011

2010

Adaptation in P300 Brain-Computer Interfaces: A Two-Classifier Cotraining Approach.

Rajesh Chandrasekhara Panicker, Sadasivan Puthusserypady, Ying Sun

IEEE Trans. Biomed. Eng., 2010

Asynchronous P300 BCI: SSVEP-based control state detection.

Rajesh Chandrasekhara Panicker, Sadasivan Puthusserypady, Ananda P. Pryana, Ying Sun

Proceedings of the 18th European Signal Processing Conference, 2010

2007

A Constrained Genetic Algorithm for Efficient Dimensionality Reduction for Pattern Classification.

Rajesh Chandrasekhara Panicker, Sadasivan Puthusserypady

Proceedings of the Computational Intelligence and Security, International Conference, 2007