Rajesh Chandrasekhara Panicker

According to our database1, Rajesh Chandrasekhara Panicker authored at least 7 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2013
Project-Based Learning in Embedded Systems Education Using an FPGA Platform.
IEEE Trans. Educ., 2013

2012
Development of an FPGA-based real-time P300 speller.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
An Asynchronous P300 BCI With SSVEP-Based Control State Detection.
IEEE Trans. Biomed. Eng., 2011

2010
Adaptation in P300 Brain-Computer Interfaces: A Two-Classifier Cotraining Approach.
IEEE Trans. Biomed. Eng., 2010

Asynchronous P300 BCI: SSVEP-based control state detection.
Proceedings of the 18th European Signal Processing Conference, 2010

2007
A Constrained Genetic Algorithm for Efficient Dimensionality Reduction for Pattern Classification.
Proceedings of the Computational Intelligence and Security, International Conference, 2007


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