Rajendran Panda
According to our database1,
Rajendran Panda
authored at least 59 papers
between 1997 and 2010.
Collaborative distances:
Collaborative distances:
Timeline
1998
2000
2002
2004
2006
2008
2010
0
5
10
1
2
1
2
2
3
2
1
1
3
3
2
2
4
7
7
1
8
1
4
2
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2010
Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Int. J. Parallel Program., 2010
2009
<i>A Special Issue on the</i> "22nd IEEE International Conference on VLSI Design" New Delhi, India, 5-9 January 2009.
J. Low Power Electron., 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
2008
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
2007
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming.
Proceedings of the 43rd Design Automation Conference, 2006
Stochastic variational analysis of large power grids considering intra-die correlations.
Proceedings of the 43rd Design Automation Conference, 2006
2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 2005 Design, 2005
2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE Des. Test Comput., 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Proceedings of the 2003 International Symposium on Physical Design, 2003
Table look-up based compact modeling for on-chip interconnect timing and noise analysis.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Duet: an accurate leakage estimation and optimization tool for dual-V<sub>t</sub> circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model .
Proceedings of the 2002 Design, 2002
2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of the 37th Conference on Design Automation, 2000
1999
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing.
Proceedings of the 36th Conference on Design Automation, 1999
1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
Proceedings of the 1998 Design, 1998
Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization.
Proceedings of the 35th Conference on Design Automation, 1998
Proceedings of the 35th Conference on Design Automation, 1998
1997
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Proceedings of the 34st Conference on Design Automation, 1997