Rajendra Bishnoi

Jan Andrés Galvan Hernández

IEEE Access, 2024

Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

A Lightweight Architecture for Real-Time Neuronal-Spike Classification.

[BibT_eX]

[DOI]

Muhammad Ali Siddiqi

David Vrijenhoek

Lennart P. L. Landsmeer

Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

Dynamic Detection and Mitigation of Read-disturb for Accurate Memristor-based Neural Networks.

[BibT_eX]

[DOI]

Sumit Diware

Mohammad Amin Yaldagard

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

Accurate and Energy-Efficient Bit-Slicing for RRAM-Based Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput. Intell., February, 2023

Severity-Based Hierarchical ECG Classification Using Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., February, 2023

On the Reliability of RRAM-Based Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

Energy-efficient Computation-In-Memory Architecture using Emerging Technologies.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Microelectronics, 2023

Dependability of Future Edge-AI Processors: Pandora's Box.

[BibT_eX]

[DOI]

Jan Richter-Brockmann

Proceedings of the IEEE European Test Symposium, 2023

Memristor-Based Lightweight Encryption.

[BibT_eX]

[DOI]

Muhammad Ali Siddiqi

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

PetaOps/W edge-AI $\mu$ Processors: Myth or reality?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Read-disturb Detection Methodology for RRAM-based Computation-in-Memory Architecture.

[BibT_eX]

[DOI]

Mohammad Amin Yaldagard

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

A 115.1 TOPS/W, 12.1 TOPS/mm<sup>2</sup> Computation-in-Memory using Ring-Oscillator based ADC for Edge AI.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

Mapping-aware Biased Training for Accurate Memristor-based Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

Reliability aspects of binary vector-matrix-multiplications using ReRAM devices.

[BibT_eX]

[DOI]

Neuromorph. Comput. Eng., 2022

A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

A Survey on Memory-centric Computer Architectures.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

Defects, Fault Modeling, and Test Development Framework for RRAMs.

[BibT_eX]

[DOI]

Moritz Fieback

Guilherme Cardoso Medeiros

ACM J. Emerg. Technol. Comput. Syst., 2022

CONVOLVE: Smart and seamless design of smart edge processors.

[BibT_eX]

[DOI]

CoRR, 2022

Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2022

Referencing-in-Array Scheme for RRAM-based CIM Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

SRIF: Scalable and Reliable Integrate and Fire Circuit ADC for Memristor-Based CIM Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories.

[BibT_eX]

[DOI]

Proc. IEEE, 2021

Low-Power Memristor-Based Computing for Edge-AI Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020

A Novel Printed-Lookup-Table-Based Programmable Printed Digital Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology.

[BibT_eX]

[DOI]

Guan Ying Wang

IEEE Trans. Very Large Scale Integr. Syst., 2020

Secure STT-MRAM Bit-Cell Design Resilient to Differential Power Analysis Attacks.

[BibT_eX]

[DOI]

Samir Ben Dodo

IEEE Trans. Very Large Scale Integr. Syst., 2020

Approximate Spintronic Memories.

[BibT_eX]

[DOI]

Mehdi B. Tahoori

ACM J. Emerg. Technol. Comput. Syst., 2020

Crossover-aware Placement and Routing for Inkjet Printed Circuits.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2020

Mitigating Read Failures in STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis.

[BibT_eX]

[DOI]

Ying Wang

Huawei Li

Said Hamdioui

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Testing Scouting Logic-Based Computation-in-Memory Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2020

A Universal Spintronic Technology based on Multifunctional Standardized Stack.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Dynamic Faults based Hardware Trojan Design in STT-MRAM.

[BibT_eX]

[DOI]

Arunkumar Vijayan

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Tolerating Retention Failures in Neuromorphic Fabric based on Emerging Resistive Memories.

[BibT_eX]

[DOI]

Christopher Münch

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Fast and Reliable STT-MRAM Using Nonuniform and Adaptive Error Detecting and Correcting Scheme.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Spintronics Memory PUF for Resilience Against Cloning Counterfeit.

[BibT_eX]

[DOI]

Samir Ben Dodo

IEEE Trans. Very Large Scale Integr. Syst., 2019

Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache Design.

[BibT_eX]

[DOI]

Longfei Mao

ACM Trans. Design Autom. Electr. Syst., 2019

A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach.

[BibT_eX]

[DOI]

Anteneh Gebregiorgis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2019

Variation-aware Fault Modeling and Test Generation for STT-MRAM.

[BibT_eX]

[DOI]

Hayk T. Grigoryan

Grigor Tshagharyan

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Predictive Modeling and Design Automation of Inorganic Printed Electronics.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Inkjet-Printed True Random Number Generator based on Additive Resistor Tuning.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Reliable in-memory neuromorphic computing using spintronics.

[BibT_eX]

[DOI]

Christopher Münch

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Inkjet-Printed EGFET-Based Physical Unclonable Function - Design, Evaluation, and Fabrication.

[BibT_eX]

[DOI]

Gabriel Cadilha Marques

Simone Dehm

IEEE Trans. Very Large Scale Integr. Syst., 2018

VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool.

[BibT_eX]

[DOI]

Fazal Hameed

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

Reliable memory PUF design for low-power applications.

[BibT_eX]

[DOI]

Saman Kiamehr

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Design and evaluation of physical unclonable function for inorganic printed electronics.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Using multifunctional standardized stack as universal spintronic technology for IoT.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A cross-layer adaptive approach for performance and power optimization in STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Parametric failure modeling and yield analysis for STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Multi-bit non-volatile spintronic flip-flop.

[BibT_eX]

[DOI]

Christopher Münch

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Spintronic normally-off heterogeneous system-on-chip design.

[BibT_eX]

[DOI]

Anteneh Gebregiorgis

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Reliable Low-Power High Performance Spintronic Memories

[BibT_eX]

[DOI]

PhD thesis, 2017

Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM cache.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Architecting SOT-RAM Based GPU Register File.

[BibT_eX]

[DOI]

Adwait Jog

Jeffrey S. Vetter

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Exploiting STT-MRAM for approximate computing.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE European Test Symposium, 2017

Opportunistic write for fast and reliable STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

VAET-STT: A variation aware estimator tool for STT-MRAM based memories.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Self-Timed Read and Write Operations in STT-MRAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing.

[BibT_eX]

[DOI]

Gilles Gaudin

IEEE Trans. Multi Scale Comput. Syst., 2016

Layout-Based Modeling and Mitigation of Multiple Event Transients.

[BibT_eX]

[DOI]

Hossein Asadi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

A cross-layer analysis of Soft Error, aging and process variation in Near Threshold Computing.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Fault Tolerant Non-Volatile spintronic flip-flop.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Non-Volatile Non-Shadow flip-flop using Spin Orbit Torque for efficient normally-off computing.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014

Read disturb fault detection in STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

Avoiding unnecessary write operations in STT-MRAM for low power implementation.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Architectural aspects in design and analysis of SOT-based memories.

[BibT_eX]

[DOI]