Rajeev R. Rao

According to our database, Rajeev R. Rao authored at least 15 papers between 2003 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

IBM POWER7+ design for higher frequency at fixed power.

Victor V. Zyuban, Scott A. Taylor, Birger Christensen, A. R. Hall, Christopher J. Gonzalez, Joshua Friedrich, Frances Clougherty, Jon Tetzloff, Rajeev R. Rao

IBM J. Res. Dev., 2013

2009

Circuit optimization techniques to mitigate the effects of soft errors in combinational logic.

Rajeev R. Rao, Vivek Joshi, David T. Blaauw, Dennis Sylvester

ACM Trans. Design Autom. Electr. Syst., 2009

2007

Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors.

Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006

Analytical yield prediction considering leakage/performance correlation.

Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Logic SER Reduction through Flipflop Redesign.

Vivek Joshi, Rajeev R. Rao, David T. Blaauw, Dennis Sylvester

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Soft error reduction in combinational logic using gate resizing and flipflop selection.

Rajeev R. Rao, David T. Blaauw, Dennis Sylvester

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

An efficient static algorithm for computing the soft error rates of combinational circuits.

Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Bus encoding for total power reduction using a leakage-aware buffer configuration.

Rajeev R. Rao, Harmander Deogun, David T. Blaauw, Dennis Sylvester

IEEE Trans. Very Large Scale Integr. Syst., 2005

Modeling and Analysis of Parametric Yield under Power and Performance Constraints.

Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Anirudh Devgan

IEEE Des. Test Comput., 2005

An efficient surface-based low-power buffer insertion algorithm.

Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif

Proceedings of the 2005 International Symposium on Physical Design, 2005

2004

Statistical analysis of subthreshold leakage current for VLSI circuits.

Rajeev R. Rao, Ashish Srivastava, David T. Blaauw, Dennis Sylvester

IEEE Trans. Very Large Scale Integr. Syst., 2004

Parametric yield estimation considering leakage variability.

Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester

Proceedings of the 41th Design Automation Conference, 2004

Leakage-and crosstalk-aware bus encoding for total power reduction.

Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David T. Blaauw

Proceedings of the 41th Design Automation Conference, 2004

2003

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation.

Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David T. Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge

Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Statistical estimation of leakage current considering inter- and intra-die process variation.

Rajeev R. Rao, Ashish Srivastava, David T. Blaauw, Dennis Sylvester

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003