Rajeev Malik

According to our database, Rajeev Malik authored at least 3 papers between 2005 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM.

Gregory Freeman, Paul Chang, E. R. Engbrecht, K. J. Giewont, David F. Hilscher, M. Lagus, Timothy J. McArdle, B. Morgenfeld, Shreesh Narasimha, James P. Norum, K. A. Nummy, Paul C. Parries, G. Wang, Jonathan K. Winslow, Paul D. Agnello, Rajeev Malik

IBM J. Res. Dev., 2015

2012

Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond.

Balaji Jayaraman, Sneha Gupta, Yanli Zhang, Puneet Goyal, Herbert Ho, Rishikesh Krishnan, Sunfei Fang, Sungjae Lee, Douglas Daley, Kevin McStay, Bernhard Wunder, John Barth, Sadanand Deshpande, Paul C. Parries, Rajeev Malik, Paul D. Agnello, Scott R. Stiffler, Subramanian S. Iyer

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2005

Strain for CMOS performance improvement.

Victor Chan, Ken Rim, Meikei Ieong, Sam Yang, Rajeev Malik, Young Way Teh, Min Yang, Qiqing Ouyang

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005