Rajeev Balasubramonian

Proceedings of the IEEE Symposium on Security and Privacy, 2024

PATHFINDER: Practical Real-Time Learning for Data Prefetching.

[BibT_eX]

[DOI]

Lin Jia

James Patrick Mcmahon

Shreyas Singh

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023

XCRYPT: Accelerating Lattice-Based Cryptography With Memristor Crossbar Arrays.

[BibT_eX]

[DOI]

Sarabjeet Singh

Xiong Fan

Ananth Krishna Prasad

Lin Jia

Mahdi Nazm Bojnordi

Elaine Shi

IEEE Micro, 2023

2022

Efficient Oblivious Query Processing for Range and kNN Queries.

[BibT_eX]

[DOI]

IEEE Trans. Knowl. Data Eng., 2022

Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion.

[BibT_eX]

[DOI]

Amlan Ganguly

Sergi Abadal

Ishan G. Thakkar

Natalie Enright Jerger

Marc D. Riedel

Masoud Babaie

Abu Sebastian

Sudeep Pasricha

Baris Taskin

IEEE Micro, 2022

Efficient and Oblivious Query Processing for Range and kNN Queries (Extended Abstract).

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Data Engineering, 2022

CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration.

[BibT_eX]

[DOI]

Sarabjeet Singh

Visvesh Sathe

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021

OrderLight: Lightweight Memory-Ordering Primitive for Efficient Fine-Grained PIM Computations.

[BibT_eX]

[DOI]

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication.

[BibT_eX]

[DOI]

Adarsh Patil

Vijay Nagarajan

Nicolai Oswald

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

ONT-X: An FPGA Approach to Real-time Portable Genomic Analysis.

[BibT_eX]

[DOI]

C. N. Ramachandra

Gurpreet S. Kalsi

Kamlesh R. Pillai

Sreenivas Subramoney

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020

Compact Leakage-Free Support for Integrity and Reliability.

[BibT_eX]

[DOI]

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks.

[BibT_eX]

[DOI]

Pierre-Emmanuel Gaillardon

Edouard Giacomin

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019

Innovations in the Memory System

[BibT_eX]

[DOI]

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01763-6, 2019

GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment.

[BibT_eX]

[DOI]

C. N. Ramachandra

Pierre-Emmanuel Gaillardon

Ryan Stutsman

Edouard Giacomin

Hari Kambalasubramanyam

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Wire-Aware Architecture and Dataflow for CNN Accelerators.

[BibT_eX]

[DOI]

Pierre-Emmanuel Gaillardon

Edouard Giacomin

Hari Kambalasubramanyam

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

The POP Detector: A Lightweight Online Program Phase Detection Framework.

[BibT_eX]

[DOI]

James Greensky

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

ρ: Relaxed Hierarchical ORAM.

[BibT_eX]

[DOI]

Chandrasekhar Nagarajan

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018

Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration.

[BibT_eX]

[DOI]

IEEE Micro, 2018

Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration.

[BibT_eX]

[DOI]

Vivek Srikumar

CoRR, 2018

An MLP-aware leakage-free memory controller.

[BibT_eX]

[DOI]

Andrew Vuong

Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018

Secure DIMM: Moving ORAM Primitives Closer to Memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

A Case for Dynamic Activation Quantization in CNNs.

[BibT_eX]

[DOI]

Proceedings of the 1st Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications, 2018

Moving CNN Accelerator Computations Closer to Data.

[BibT_eX]

[DOI]

Proceedings of the 1st Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications, 2018

VAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017

CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2017

INXS: Bridging the throughput and energy gap for spiking neural networks.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Introspective Computing.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016

Near-Data Processing [Guest editors' introduction].

[BibT_eX]

[DOI]

Boris Grot

IEEE Micro, 2016

Addressing service interruptions in memory with thread-to-rank assignment.

[BibT_eX]

[DOI]

Jung-Sik Kim

Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Understanding and alleviating intra-die and intra-DIMM parameter variation in the memory system.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Enabling technologies for memory compression: Metadata, mapping, and prediction.

[BibT_eX]

[DOI]

Robert Schreiber

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015

Efficiently prefetching complex address patterns.

[BibT_eX]

[DOI]

Sahil Koladiya

Chris Wilkerson

Zeshan Chishti

Proceedings of the 48th International Symposium on Microarchitecture, 2015

Avoiding information leakage in the memory controller with fixed service policies.

[BibT_eX]

[DOI]

Akhila Gundu

Proceedings of the 48th International Symposium on Microarchitecture, 2015

Improving memristor memory with sneak current sharing.

[BibT_eX]

[DOI]

Yoocharn Jeon

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Fixed-function hardware sorting accelerators for near data MapReduce execution.

[BibT_eX]

[DOI]

Arjun Deb

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Overcoming the challenges of crossbar resistive memory architectures.

[BibT_eX]

[DOI]

Cong Xu

Dimin Niu

Tao Zhang

Shimeng Yu

Yuan Xie

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014

Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads.

[BibT_eX]

[DOI]

Jeffrey Jestes

Vijayalakshmi Srinivasan

IEEE Micro, 2014

Near-Data Processing: Insights from a MICRO-46 Workshop.

[BibT_eX]

[DOI]

IEEE Micro, 2014

Managing DRAM Latency Divergence in Irregular GPGPU Applications.

[BibT_eX]

[DOI]

Proceedings of the International Conference for High Performance Computing, 2014

NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads.

[BibT_eX]

[DOI]

Jeffrey Jestes

Huihui Zhang

Vijayalakshmi Srinivasan

Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

Memory bandwidth reservation in the cloud to avoid information leakage in the memory controller.

[BibT_eX]

[DOI]

Proceedings of the HASP 2014, 2014

MemZip: Exploring unconventional benefits from memory compression.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013

Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device.

[BibT_eX]

[DOI]

Jung-Sik Kim

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

A novel system architecture for web scale applications using lightweight CPUs and virtualized I/O.

[BibT_eX]

[DOI]

Saisanthosh Balakrishnan

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012

Managing Data Placement in Memory Systems with Multiple Memory Controllers.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2012

Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access.

[BibT_eX]

[DOI]

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems.

[BibT_eX]

[DOI]

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Staged Reads: Mitigating the impact of DRAM writes on DRAM reads.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Efficient scrub mechanisms for error-prone emerging memories.

[BibT_eX]

[DOI]

Viji Srinivasan

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Optimizing datacenter power with memory system levers for guaranteed quality-of-service.

[BibT_eX]

[DOI]

Sadagopan Srinivasan

Ravi R. Iyer

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011

Multi-Core Cache Hierarchies

[BibT_eX]

[DOI]

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01734-6, 2011

Buses and Crossbars.

[BibT_eX]

[DOI]

Timothy Mark Pinkston

Proceedings of the Encyclopedia of Parallel Computing, 2011

CHOP: Integrating DRAM Caches for CMP Server Platforms.

[BibT_eX]

[DOI]

IEEE Micro, 2011

Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems.

[BibT_eX]

[DOI]

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Understanding the Behavior of Pthread Applications on Non-Uniform Cache Architectures.

[BibT_eX]

[DOI]

Gagandeep S. Sachdev

Mary W. Hall

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Prediction Based DRAM Row-Buffer Management in the Many-Core Era.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010

Hardware prediction of OS run-length for fine-grained resource customization.

[BibT_eX]

[DOI]

Erik Brunvand

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010

Rethinking DRAM design and organization for energy-constrained multi-cores.

[BibT_eX]

[DOI]

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Improving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality.

[BibT_eX]

[DOI]

Erik Brunvand

Proceedings of the Computer Architecture, 2010

Towards scalable, energy-efficient, bus-based on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

CHOP: Adaptive filter-based DRAM caching for CMP server platforms.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Micro-pages: increasing DRAM efficiency with locality-aware data placement.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

SWEL: hardware cache coherence protocols to map shared data onto shared caches.

[BibT_eX]

[DOI]

Josef B. Spjut

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

Handling the problems and opportunities posed by multiple on-chip memory controllers.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009

OS execution on multi-cores: is out-sourcing worthwhile?

[BibT_eX]

[DOI]

Erik Brunvand

ACM SIGOPS Oper. Syst. Rev., 2009

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.

[BibT_eX]

[DOI]

Ravishankar R. Iyer

Srihari Makineni

Donald Newell

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches.

[BibT_eX]

[DOI]

John B. Carter

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Non-uniform power access in large caches with low-swing wires.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on High Performance Computing, 2009

2008

Architecting Efficient Interconnects for Large Caches with CACTI 6.0.

[BibT_eX]

[DOI]

IEEE Micro, 2008

Scalable and reliable communication for hardware transactional memory.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007

Power Efficient Approaches to Redundant Multithreading.

[BibT_eX]

[DOI]

Niti Madan

IEEE Trans. Parallel Distributed Syst., 2007

Understanding the Impact of 3D Stacked Layouts on ILP.

[BibT_eX]

[DOI]

Vivek Venkatesan

J. Instr. Level Parallelism, 2007

Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Leveraging 3D Technology for Improved Reliability.

[BibT_eX]

[DOI]

Niti Madan

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Interconnect design considerations for large NUCA caches.

[BibT_eX]

[DOI]

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006

Leveraging Wire Properties at the Microarchitecture Level.

[BibT_eX]

[DOI]

IEEE Micro, 2006

Power efficient resource scaling in partitioned architectures through dynamic heterogeneity.

[BibT_eX]

[DOI]

Karthik Ramani

Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Interconnect-Aware Coherence Protocols for Chip Multiprocessors.

[BibT_eX]

[DOI]

Liqun Cheng

Karthik Ramani

John B. Carter

Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

2005

Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.

[BibT_eX]

[DOI]

Venkatanand Venkatachalapathy

Karthik Ramani

Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004

Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures.

[BibT_eX]

[DOI]

Proceedings of the 18th Annual International Conference on Supercomputing, 2004

2003

A Dynamically Tunable Memory Hierarchy.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2003

Dynamically Tuning Processor Resources with Adaptive Processing.

[BibT_eX]

[DOI]

Computer, 2003

Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches.

[BibT_eX]

[DOI]

Viji Srinivasan

Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003

Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors.

[BibT_eX]

[DOI]

Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

2002

Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.

[BibT_eX]

[DOI]

Greg Semeraro

Grigorios Magklis

Michael L. Scott

Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power.

[BibT_eX]

[DOI]

Steve Dropsho

Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001

Reducing the complexity of the register file in dynamic superscalar processors.

[BibT_eX]

[DOI]

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Dynamically allocating processor resources between nearby and distant ILP.

[BibT_eX]

[DOI]

Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

2000

Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures.

[BibT_eX]

[DOI]