Rajashekar B. Shettar

Orcid: 0000-0002-0240-1647

According to our database1, Rajashekar B. Shettar authored at least 4 papers between 2015 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
A Power-Efficient and Quantum-Resistant N-Bit Cryptography Algorithm.
Int. J. Nat. Comput. Res., 2020

2018
A Novel Design and Implementation of 8-Bit and 16-Bit Hybrid ALU.
Proceedings of the Intelligent Systems Design and Applications, 2018

2016
Open Ended Approach to Empirical Learning of IOT with Raspberry Pi in Modeling and Simulation Lab.
Proceedings of the Eighth IEEE International Conference on Technology for Education, 2016

2015
Design of area efficient and low power bandgap voltage reference using sub-threshold MOS transistors.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015


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