Rajasekhar Nagulapalli

Orcid: 0000-0003-0526-3232

According to our database1, Rajasekhar Nagulapalli authored at least 28 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Wide Range Constant Transconductance Circuit Based on Negative Feedback for Analog Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency.
J. Circuits Syst. Comput., March, 2023

Dynamic Averager Based Sub-1V Bandgap Voltage Reference.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022
A Novel Sub-1V Bandgap Reference with 17.1 ppm/<sup>0</sup>C Temperature coefficient in 28nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A 24.4 ppm/°C Voltage Mode Bandgap Reference With a 1.05V Supply.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 82μW Mixed-Mode sub-1V Bandgap reference with 25 ppm/°C Temperature Co-efficient with Simultaneous PTAT Generation.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

A Novel 22.7 ppm/<sup>0</sup>C Voltage mode Sub-Bandgap Reference with robust startup nature.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 15uW, 12 ppm/<sup>°</sup>C Curvature Compensated Bandgap in 0.85V Supply.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A High-Sensitivity and Low-Power Circuit for the Measurement of Abnormal Blood Cell Levels.
J. Circuits Syst. Comput., 2020

A Positive Feedback-Based Op-Amp Gain Enhancement Technique for High-Precision Applications.
J. Circuits Syst. Comput., 2020

A VGA Linearity Improvement Technique for ECG Analog Front-End in 65nm CMOS.
J. Circuits Syst. Comput., 2020

A two-stage opamp frequency Compensation technique by splitting the 2<sup>nd</sup> stage.
Proceedings of the 11th International Conference on Computing, 2020

A Single BJT 10.2 ppm/°C Bandgap Reference in 45nm CMOS Technology.
Proceedings of the 11th International Conference on Computing, 2020

2019
A Start-up Assisted Fully Differential Folded Cascode Opamp.
J. Circuits Syst. Comput., 2019

A Low Noise Amplifier Suitable for Biomedical Recording Analog Front-End in 65nm CMOS Technology.
J. Circuits Syst. Comput., 2019

A 0.55 V Bandgap Reference with a 59 ppm/°C Temperature Coefficient.
J. Circuits Syst. Comput., 2019

A High Value, Linear and Tunable CMOS Pseudo-Resistor for Biomedical Applications.
J. Circuits Syst. Comput., 2019

A CMOS Self-Bias CTAT Current Generator with Improved Supply Sensitivity.
J. Circuits Syst. Comput., 2019

A High-Performance Skin Impedance Measurement Circuit for Biomedical Applications.
J. Circuits Syst. Comput., 2019

A High Frequency CMRR improvement technique for Differential Amplifiers in 45nm CMOS.
Proceedings of the 10th International Conference on Computing, 2019

A Low Power Miller Compensation Technique for Two Stage Op-amp in 65nm CMOS Technology.
Proceedings of the 10th International Conference on Computing, 2019

2018
A 0.6 V MOS-Only Voltage Reference for Biomedical Applications with 40 ppm/∘C Temperature Drift.
J. Circuits Syst. Comput., 2018

A 31 ppm/° C Pure CMOS Bandgap Reference by Exploiting Beta-Multiplier.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

High Performance Circuit Techniques for Nueral Front-End Design in 65nm CMOS.
Proceedings of the 9th International Conference on Computing, 2018

A Technique to Reduce the Capacitor Size in Two Stage Miller Compensated Opamp.
Proceedings of the 9th International Conference on Computing, 2018

2016
23.5 A dual 64Gbaud 10kΩ 5% THD linear differential transimpedance amplifier with automatic gain control in 0.13µm BiCMOS technology for optical fiber coherent receivers.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2010
High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010


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