Rajarshee P. Bharadwaj

According to our database, Rajarshee P. Bharadwaj authored at least 5 papers between 2005 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

Exploring Logic Block Granularity in Leakage Tolerant FPGA.

Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A leakage aware design methodology for power-gated programmable architectures.

Narayan Subramanian, Rajarshee P. Bharadwaj, Dinesh Bhatia

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2005

FPGA Architecture for Standby Power Management.

Rajarshee P. Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras T. Balsara

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Next Generation Architectures and CAD for Power Aware Programmable Fabrics.

Rajarshee P. Bharadwaj

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Exploiting temporal idleness to reduce leakage power in programmable architectures.

Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005