Raj Varada

According to our database¹, Raj Varada authored at least 8 papers between 2006 and 2015.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

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Bibliography

2015

A 22 nm 15-Core Enterprise Xeon® Processor Family.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

2014

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2010

A 45 nm 8-Core Enterprise Xeon¯ Processor.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

2009

A 45nm 8-core enterprise Xeon® processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Power reduction techniques for an 8-core xeon® processor.

[BibT_eX]

[DOI]

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2007

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

2006

SOC Design Challenges in a Multi-threaded 65nm Dual Core Xeon® MP Processor.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Design and integration methods for a multi-threaded dual core 65nm Xeon® processor.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Raj Varada

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