Rainer Ohlendorf

According to our database¹, Rainer Ohlendorf authored at least 15 papers between 2005 and 2011.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

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2011

A network processor architecture with application-optimized reconfigurable processing paths (FlexPath NP).

[BibT_eX]

[DOI]

Rainer Ohlendorf

PhD thesis, 2011

Hardware Support for Efficient Resource Utilization in Manycore Processor Systems.

[BibT_eX]

[DOI]

Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010

An Application-Aware Load Balancing Strategy for Network Processors.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2010

FlexPath NP - Flexible, Dynamically Reconfigurable Processing Paths in Network Processors.

[BibT_eX]

[DOI]

Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009

An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

A Processing Path Dispatcher in Network Processor MPSoCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

FlexPath NP - A network processor architecture with flexible processing paths.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Network processors.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

A Hardware Packet Re-Sequencer Unit for Network Processors.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems, 2008

2007

Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

A Programmable Stream Processing Engine for Packet Manipulation in Network Processors.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006

Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications.

[BibT_eX]

[DOI]

Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Performance evaluation for system-on-chip architectures using trace-based transaction level simulation.

[BibT_eX]

[DOI]

Thomas Wild

Andreas Herkersdorf

Rainer Ohlendorf

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Reconfigurable Processing Units vs. Reconfigurable Interconnects.

[BibT_eX]

[DOI]

Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

2005

FlexPath NP: a network processor concept with application-driven flexible processing paths.

[BibT_eX]

[DOI]

Rainer Ohlendorf

Andreas Herkersdorf

Thomas Wild

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Rainer Ohlendorf

Timeline

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Bibliography

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