Rainer Leupers

IEEE Trans. Very Large Scale Integr. Syst., 2016

Parallel SystemC Simulation for ESL Design.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2016

Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2016

MPSoC Software Debugging on Virtual Platforms via Execution Control with Event Graphs.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2016

A Scalable, Multimode SVD Precoding ASIC Based on the Cyclic Jacobi Method.

[BibT_eX]

[DOI]

Daniel Günther

Maria H. Rodriguez Blanco

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms.

[BibT_eX]

[DOI]

J. Syst. Archit., 2016

An optimal allocation of memory buffers for complex multicore platforms.

[BibT_eX]

[DOI]

J. Syst. Archit., 2016

Black box ESL power estimation for loosely-timed TLM models.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Concurrent memory subsystem and application optimization for ASIP design.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Automatic recognition of computational kernels for platform-dependent code optimizations.

[BibT_eX]

[DOI]

Georg Reinke

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

ORVD-Trellis based MIMO detection.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

A flexible MCMC detector ASIC.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

Black box power estimation for digital signal processors using virtual platforms.

[BibT_eX]

[DOI]

Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation, 2016

SystemC-link: Parallel SystemC simulation using time-decoupled segments.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Technology Transfer in computing systems: The TETRACOM approach.

[BibT_eX]

[DOI]

Dimitrios S. Nikolopoulos

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Mantissa-masking for energy-efficient floating-point LTE uplink MIMO baseband processing.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting.

[BibT_eX]

[DOI]

Cosmin Cernazanu-Glavan

Lucian Bara

Marian Ionascu

Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015

Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIP.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design.

[BibT_eX]

[DOI]

Juan Fernando Eusse Giraldo

Christopher Williams

ACM Trans. Reconfigurable Technol. Syst., 2015

Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture.

[BibT_eX]

[DOI]

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Enhanced GPU Resource Utilization through Fairness-aware Task Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015

Modeling Exclusive Memory Access for a Time-Decoupled Parallel SystemC Simulator.

[BibT_eX]

[DOI]

Jan Henrik Weinstock

Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation.

[BibT_eX]

[DOI]

Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

A Toolflow for Parallelization of Embedded Software in Multicore DSP Platforms.

[BibT_eX]

[DOI]

Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Parallel SystemC simulation for ESL design using flexible time decoupling.

[BibT_eX]

[DOI]

Jan Henrik Weinstock

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

ESL power estimation using virtual platforms with black box processor models.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Deterministic event-based control of Virtual Platforms for MPSoC software debugging.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Parallelism extraction in embedded software for android devices.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Design and synthesis of reconfigurable control-flow structures for CGRA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A comparative investigation of device-specific mechanisms for exploiting HPC accelerators.

[BibT_eX]

[DOI]

Ayman Tarakji

Lukas Börger

Proceedings of the 8th Workshop on General Purpose Processing using GPUs, 2015

Buffer Allocation Based On-Chip Memory Optimization for Many-Core Platforms.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Direct FPGA-based power profiling for a RISC processor.

[BibT_eX]

[DOI]

Cosmin Cernazanu-Glavan

Proceedings of the 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2015

Extraction of Kahn Process Networks from While Loops in Embedded Software.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface.

[BibT_eX]

[DOI]

Proceedings of the 2015 Forum on Specification and Design Languages, 2015

Multi/many-core programming: where are we standing?

[BibT_eX]

[DOI]

Mauricio Alvarez-Mesa

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Parallel Density-Based Stream Clustering Using a Multi-user GPU Scheduler.

[BibT_eX]

[DOI]

Proceedings of the Beyond Databases, Architectures and Structures, 2015

SWAT: Assertion-based debugging of concurrency issues at system level.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Unified Identification of Multiple Forms of Parallelism in Embedded Applications.

[BibT_eX]

[DOI]

Miguel Angel Aguilar

Juan Fernando Eusse Giraldo

Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014

legaSCi: Legacy SystemC Model Integration into Parallel Simulators.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

A compiler infrastructure for embedded heterogeneous MPSoCs.

[BibT_eX]

[DOI]

Parallel Comput., 2014

A Parallel MCMC-Based MIMO Detector: VLSI Design and Algorithm.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

VLSI design of a parallel MCMC-based MIMO detector with multiplier-free Gibbs samplers.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Improving ESL power models using switching activity information from timed functional models.

[BibT_eX]

[DOI]

Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, 2014

Pre-architectural performance estimation for ASIP design based on abstract processor models.

[BibT_eX]

[DOI]

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

A Novel Class of Linear MIMO Detectors with Boosted Communications Performance: Algorithm and VLSI Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Energy-efficiency of floating-point and fixed-point SIMD cores for MIMO processing systems.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on System-on-Chip, 2014

EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems.

[BibT_eX]

[DOI]

Lars Schor

Iuliana Bacivarov

Luis Gabriel Murillo

Pier Stanislao Paolucci

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Efficient VLSI architectures for matrix inversion in soft-input soft-output MMSE MIMO detectors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A heuristic for logical data buffer allocation in multicore platforms.

[BibT_eX]

[DOI]

Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014

A novel reduced-complexity soft-input soft-output MMSE MIMO detector: Algorithm and efficient VLSI architecture.

[BibT_eX]

[DOI]

Gerd H. Ascheid

Proceedings of the IEEE International Conference on Communications, 2014

VLSI implementation of linear MIMO detection with boosted communications performance: extended abstract.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Time-decoupled parallel SystemC simulation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Optimized buffer allocation in multicore platforms.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Automatic detection of concurrency bugs through event ordering constraints.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Technology transfer towards Horizon 2020.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A flexible ASIP architecture for connected components labeling in embedded vision applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Software Compilation Techniques for MPSoCs.

[BibT_eX]

[DOI]

Weihua Sheng

Proceedings of the Handbook of Signal Processing Systems, 2013

MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Informatics, 2013

Efficient Implementation of Application-Aware Spinlock Control in MPSoCs.

[BibT_eX]

[DOI]

Int. J. Embed. Real Time Commun. Syst., 2013

Automatic Calibration of Streaming Applications for Software Mapping Exploration.

[BibT_eX]

[DOI]

IEEE Des. Test, 2013

EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment

[BibT_eX]

[DOI]

Pier Stanislao Paolucci

CoRR, 2013

DSPACE hardware architecture for on-board real-time image/video processing in European space missions.

[BibT_eX]

[DOI]

Proceedings of the Real-Time Image and Video Processing 2013, 2013

Mapping of MIMO Receiver Algorithms onto Application-Specific Multi-Core Platforms.

[BibT_eX]

[DOI]

Daniel Günther

Proceedings of the ISWCS 2013, 2013

Split-cost communication model for improved MPSoC application mapping.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on System on Chip, 2013

legaSCi: Legacy SystemC Model Integration into Parallel Systemc Simulators.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Embedded Real-Time Application Prototyping Using a Hybrid Multiprocessing Platform.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013

Creation of ESL power models for communication architectures using automatic calibration.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A New Space Digital Signal Processor Design.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2013

2012

Throughput driven transformations of Synchronous Data Flows for mapping to heterogeneous MPSoCs.

[BibT_eX]

[DOI]

Anastasia Stulova

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 Platform: Case Study and Optimizations.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

Application-aware spinlock control using a hardware scheduler in MPSoC platforms.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Symposium on System on Chip, 2012

Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

SCandal: SystemC Analysis for Nondeterminism Anomalies.

[BibT_eX]

[DOI]

Proceedings of the Models, Methods, and Tools for Complex Chip Design, 2012

Virtual platforms: Breaking new grounds.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Hybrid simulation for extensible processor cores.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Synchronization for hybrid MPSoC full-system simulation.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Communication-aware mapping of KPN applications onto heterogeneous MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Fast graph-based instruction selection for multi-output instructions.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 2011

Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis.

[BibT_eX]

[DOI]

Int. J. Embed. Real Time Commun. Syst., 2011

Checkpointing SystemC-Based Virtual Platforms.

[BibT_eX]

[DOI]

Int. J. Embed. Real Time Commun. Syst., 2011

A retargetable framework for compiler/architecture co-development.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2011

Enhanced structural analysis for C code reconstruction from IR code.

[BibT_eX]

[DOI]

Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems, 2011

Trends in embedded software synthesis.

[BibT_eX]

[DOI]

Weihua Sheng

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Virtual Manycore platforms: Moving towards 100+ processor cores.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Analytical and Simulation-based Design Space Exploration of Software Defined Radios.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2010

Automatic Generation of Memory Interfaces for ASIPs.

[BibT_eX]

[DOI]

Int. J. Embed. Real Time Commun. Syst., 2010

System level MPSoC design: a bright future for compiler technology?

[BibT_eX]

[DOI]

Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, 2010

2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.

[BibT_eX]

[DOI]

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Optimized communication architecture of MPSoCs with a hardware scheduler: A system view.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

Towards Network Centric Development of Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of IEEE International Conference on Communications, 2010

Cool MPSoC programming.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

parSC: synchronous parallel systemc simulation on multi-core host architectures.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

MPSoC programming using the MAPS compiler.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Software Compilation Techniques for MPSoCs.

[BibT_eX]

[DOI]

Weihua Sheng

Proceedings of the Handbook of Signal Processing Systems, 2010

2009

A SIMD optimization framework for retargetable compilers.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2009

Integrated verification approach during ADL-driven processor design.

[BibT_eX]

[DOI]

Microelectron. J., 2009

Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2009

A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding

[BibT_eX]

[DOI]

CoRR, 2009

A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE International Conference on Secure Software Integration and Reliability Improvement, 2009

A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs).

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2009

A checkpoint/restore framework for systemc-based virtual platforms.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

Automatic generation of memory interfaces.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

Task management in MPSoCs: An ASIP approach.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Programming MPSoC platforms: Road works ahead!

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

TotalProf: a fast and accurate retargetable source code profiler.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

A high-level virtual platform for early MPSoC software development.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008

A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2008

Power-efficient Instruction Encoding Optimization for Various Architecture Classes.

[BibT_eX]

[DOI]

J. Comput., 2008

SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends.

[BibT_eX]

[DOI]

Int. J. Embed. Syst., 2008

Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips.

[BibT_eX]

[DOI]

Int. J. Embed. Syst., 2008

System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Retargetable Code Optimization for Predicated Execution.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Multiprocessor performance estimation using hybrid simulation.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

MAPS: an integrated framework for MPSoC application parallelization.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

ASIP architecture exploration for efficient IPSec encryption: A case study.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2007

Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Increasing data-bandwidth to instruction-set extensions through register clustering.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Design space exploration of partially re-configurable embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A code-generator generator for multi-output instructions.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

HySim: a fast simulation framework for embedded software development.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

A fast and generic hybrid simulation approach using C virtual machine.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Compilers, 2007

Optimized ASIP synthesis from architecture description language models.

[BibT_eX]

[DOI]

Oliver Schliebusch

Heinrich Meyr

Kluwer, ISBN: 978-1-4020-5685-7, 2007

2006

Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2006

Offset assignment using simultaneous variable coalescing.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2006

Memory Access Micro-Profiling for ASIP Design.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

An interprocedural code optimization technique for network processors using hardware multi-threading support.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A design flow for configurable embedded processors based on optimized instruction set extension synthesis.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A SW performance estimation framework for early system-level-design using fine-grained instrumentation.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Design and implementation of a modular and portable IEEE 754 compliant floating-point unit.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

ASIP design and synthesis for non linear filtering in image processing.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Automatic ADL-based operand isolation for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

An integrated open framework for heterogeneous MPSoC design space exploration.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

SHAPES: : a tiled scalable software hardware architecture platform for embedded systems.

[BibT_eX]

[DOI]

Pier Stanislao Paolucci

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Retargetable code optimization with SIMD instructions.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Integrated system-level modeling of network-on-chip enabled multi-processor platforms.

[BibT_eX]

[DOI]

Tim Kogel

Mohammad Abdullah Al Faruque

Heinrich Meyr

Kluwer, ISBN: 978-1-4020-4825-8, 2006

2005

Optimization Techniques for ADL-Driven RTL Processor Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

C Compiler Retargeting Based on Instruction Semantics Models.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Fine-grained application source code profiling for ASIP design.

[BibT_eX]

[DOI]

Kingshuk Karuri

Proceedings of the 42nd Design Automation Conference, 2005

Retargetable generation of TLM bus interfaces for MP-SoC platforms.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.

[BibT_eX]

[DOI]

Mohammad Mostafizur Rahman Mozumdar

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Digital Signal Processors.

[BibT_eX]

Proceedings of the Handbook of Networked and Embedded Control Systems, 2005

2004

A universal technique for fast and flexible instruction-set architecture simulation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Early ISS Integration into Network-on-Chip Designs.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

RTL Processor Synthesis for Architecture Exploration and Implementation.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

A novel approach for flexible and consistent ADL-driven ASIP design.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Compiler based exploration of DSP energy savings by SIMD operations.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Instruction Scheduler Generation for Retargetable Compilation.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models.

[BibT_eX]

[DOI]

Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

Improving Offset Assignment through Simultaneous Variable Coalescing.

[BibT_eX]

[DOI]

Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

Processor/Memory Co-Exploration on Multiple Abstraction Levels.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Instruction encoding synthesis for architecture exploration using hierarchical processor models.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

A modular simulation framework for architectural exploration of on-chip interconnection networks.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms.

[BibT_eX]

[DOI]

Proceedings of the Compiler Construction, 12th International Conference, 2003

2002

Compiler Design Issues for Embedded Processors.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2002

Application specific compiler/architecture codesign: a case study.

[BibT_eX]

[DOI]

Proceedings of the 2002 Joint Conference on Languages, 2002

Architecture exploration for embedded processors with LISA.

[BibT_eX]

Andreas Hoffmann

Heinrich Meyr

Kluwer, ISBN: 978-1-4020-7338-0, 2002

2001

C compiler design for a network processor.

[BibT_eX]

[DOI]

Jens Wagner

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

C Compiler Design for an Industrial Network Processor.

[BibT_eX]

[DOI]

Jens Wagner

Proceedings of the 2001 ACM SIGPLAN Workshop on Optimization of Middleware and Distributed Systems, 2001

Low-Energy DSP Code Generation Using a Genetic Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Variable partitioning for dual memory bank DSPs.

[BibT_eX]

[DOI]

Daniel Kotte

Proceedings of the IEEE International Conference on Acoustics, 2001

Optimized address assignment for DSPs with SIMD memory accesses.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

Retargetable compiler technology for embedded systems - tools and applications.

[BibT_eX]

Kluwer, ISBN: 978-0-7923-7578-4, 2001

2000

Graph-based code selection techniques for embedded processors.

[BibT_eX]

[DOI]

Steven Bashford

ACM Trans. Design Autom. Electr. Syst., 2000

Code Generation for Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the 13th International Symposium on System Synthesis, 2000

Code Selection for Media Processors with SIMD Instructions.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

Instruction Scheduling for Clustered VLIW DSPs.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000

Code optimization techniques for embedded processors - methods, algorithms, and tools.

[BibT_eX]

Kluwer, ISBN: 978-0-7923-7989-8, 2000

1999

Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths.

[BibT_eX]

[DOI]

Steven Bashford

Des. Autom. Embed. Syst., 1999

Array Index Allocation under Register Constraints in DSP Programs.

[BibT_eX]

[DOI]

Anupam Basu

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Function inlining under code size constraints for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Constraint Driven Code Selection for Fixed-Point DSPs.

[BibT_eX]

[DOI]

Steven Bashford

Proceedings of the 36th Conference on Design Automation, 1999

Generation of Interpretive and Compiled Instruction Set Simulators.

[BibT_eX]

[DOI]

Johann Elste

Birger Landwehr

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Retargetable Code Generation Based on Structural Processor Description.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 1998

A Uniform Optimization Technique for Offset Assignment Problems.

[BibT_eX]

[DOI]

Fabian David

Proceedings of the 11th International Symposium on System Synthesis, 1998

HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on System Synthesis, 1998

[BibT_eX]

[DOI]

Anupam Basu

Proceedings of the 1998 Design, 1998

Optimized Array Index Computation in DSP Programs.

[BibT_eX]

[DOI]

Anupam Basu

Proceedings of the ASP-DAC '98, 1998

1997

Time-constrained code compaction for DSPs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1997

Retargetable generation of code selectors from HDL processor models.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

Retargetable code generation for digital signal processors.

[BibT_eX]

Kluwer, ISBN: 978-0-7923-9958-2, 1997

1996

Instruction-Set Modeling for ASIP Code Generation.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Algorithms for address assignment in DSP code generation.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Instruction selection for embedded DSPs with complex instructions.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

1995

A BDD-based frontend for retargetable compilers.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

Using compilers for heterogeneous system design.

[BibT_eX]

[DOI]

Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

1994

Retargetable assembly code generation by bootstrapping.

[BibT_eX]

[DOI]

Wolfgang Schenk

Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Microcode Generation for Flexible Parallel Target Architectures.

[BibT_eX]

[DOI]

Wolfgang Schenk

Proceedings of the Parallel Architectures and Compilation Techniques, 1994

Instruction set extraction from programmable structures.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

1993

Resistance Extraction using a Routing Algorithm.

[BibT_eX]

[DOI]

Lorenz Ladage