Rahul Sreekumar

According to our database1, Rahul Sreekumar authored at least 13 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Exploring Noise- Resilient Spiking Neural Encoding using ∑†∑ Neurons.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

EASI-CiM: Event-driven Asynchronous Stream-based Image classifier with Compute-in-Memory kernels.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Double magnetic tunnel junction based ∑Δ∑ hardware neuron.
Proceedings of the Device Research Conference, 2024

2023
Virtualized Controller for Computational RFID-based IoT Sensors.
Proceedings of the IEEE International Conference on RFID, 2023

Hardware Trojans in eNVM Neuromorphic Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Processing-in-Memory with Temporal Encoding.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2021
ATCPiM: Analog to Time Coded Processing in Memory for IoT at the Edge.
Proceedings of the 7th IEEE World Forum on Internet of Things, 2021

Microarchitecture Optimization for Asynchronous Stochastic Computing.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020
Towards on-node Machine Learning for Ultra-low-power Sensors Using Asynchronous Σ Δ Streams.
ACM J. Emerg. Technol. Comput. Syst., 2020

2018
Low-Power Bluetooth Receiver Front End Design with Oscillator Leakage Reduction Technique.
J. Low Power Electron., 2018

2017
Low power comparator with offset cancellation technique for Flash ADC.
Proceedings of the 14th International Conference on Synthesis, 2017

Cascode Stage Based LNA for Bluetooth Applications in 45 nm CMOS Technology.
Proceedings of the New Generation of CAS, 2017

Bluetooth Low Energy (BLE) Direct Down Conversion Receiver Front End in 65nm CMOS Technology.
Proceedings of the New Generation of CAS, 2017


  Loading...