Rahul Boyapati

Orcid: 0000-0003-1094-485X

According to our database1, Rahul Boyapati authored at least 8 papers between 2010 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
A Voting Approach for Adaptive Network-on-Chip Power-Gating.
IEEE Trans. Computers, 2021

2019
Active-Routing: Compute on the Way for Near-Data Processing.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2017
APPROX-NoC: A Data Approximation Framework for Network-On-Chip Architectures.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Fly-Over: A Light-Weight Distributed Power-Gating Mechanism for Energy-Efficient Networks-on-Chip.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Packet coalescing exploiting data redundancy in GPGPU architectures.
Proceedings of the International Conference on Supercomputing, 2017

2016
POSTER: Fly-Over: A Light-Weight Distributed Power-Gating Mechanism For Energy-Efficient Networks-on-Chip.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Intra-Clustering: Accelerating On-chip Communication for Data Parallel Architectures.
Proceedings of the 2015 International Symposium on Computer Architecture and High Performance Computing Workshops, 2015

2010
Efficient lookahead routing and header compression for multicasting in networks-on-chip.
Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010


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