Raghuram S. Tupuri

According to our database1, Raghuram S. Tupuri authored at least 10 papers between 1992 and 2008.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2008
A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2006
Delay Constrained Register Transfer Level Dynamic Power Estimation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2003
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages.
J. Electron. Test., 2003

2002
A Comprehensive Fault Model for Deep Submicron Digital Circuits.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001
Timing Verification and Delay Test Generation for Hierarchical Designs.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000
Hierarchical Test Generation for Systems On a Chip.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999
Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor.
Proceedings of the 36th Conference on Design Automation, 1999

1997
A Novel Hierarchical Test Generation Method for Processors.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Novel Functional Test Generation Method for Processors Using Commercial ATPG.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1992
Design Migration Across Technology - Making It Work.
Proceedings of the Fifth International Conference on VLSI Design, 1992


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