Raghunandana K. K

According to our database, Raghunandana K. K authored at least 5 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

TRRR: Accelerated Online Error Detecting and Correcting Fault Tolerant Architecture.

Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh

Proceedings of the IEEE East-West Design & Test Symposium, 2024

TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection.

Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh

Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024

2023

TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture.

Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh

Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture.

Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2022

REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture.

Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022