Raghavendra Pradyumna Pothukuchi
Orcid: 0000-0003-0109-7417
According to our database1,
Raghavendra Pradyumna Pothukuchi
authored at least 23 papers
between 2016 and 2024.
Collaborative distances:
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Bibliography
2024
Distributed Brain-Computer Interfacing With a Networked Multiaccelerator Architecture.
IEEE Micro, 2024
CoRR, 2024
FriendlyFoe: Adversarial Machine Learning as a Practical Architectural Defense against Side Channel Attacks.
Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques, 2024
2023
IEEE Micro, 2023
CoRR, 2023
CoRR, 2023
A Multi-Site Accelerator-Rich Processing Fabric for Scalable Brain-Computer Interfacing.
CoRR, 2023
SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Proceedings of the 19th Workshop on Hot Topics in Operating Systems, 2023
2022
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2022
2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
2020
2019
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
Structured Singular Value Control for Modular Resource Management in Multilayer Computers.
Proceedings of the 57th IEEE Conference on Decision and Control, 2018
2017
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017
Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017
2016
Using Multiple Input, Multiple Output Formal Control to Maximize Resource Efficiency in Architectures.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016