Raghavendra B. Deshmukh

According to our database, Raghavendra B. Deshmukh authored at least 19 papers between 2006 and 2022.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2022

Optimization of elliptic curve scalar multiplication using constraint based scheduling.

Pravin Zode, Raghavendra B. Deshmukh

J. Parallel Distributed Comput., 2022

2021

Novel fault attack resistant architecture for elliptic curve cryptography.

Pravin Zode, Raghavendra B. Deshmukh

Microprocess. Microsystems, 2021

2020

A Machine Condition Monitoring Framework Using Compressed Signal Processing.

Meenu Rani, Sanjay B. Dhok, Raghavendra B. Deshmukh

Sensors, 2020

Overlap Aware Compressed Signal Classification.

Meenu Rani, Sanjay B. Dhok, Raghavendra B. Deshmukh, Punit Kumar

IEEE Access, 2020

2018

Self-compensation scheme for truncation error in fixed width multipliers.

Pankaj U. Joshi, Raghavendra B. Deshmukh, Venkateshwarlu Gudur

IET Circuits Devices Syst., 2018

A Systematic Review of Compressive Sensing: Concepts, Implementations and Applications.

Meenu Rani, Sanjay B. Dhok, R. B. Deshmukh

IEEE Access, 2018

Design and Fabrication of Versatile Low Power Wireless Sensor Nodes for IoT Applications.

Saket Thool, Raghavendra B. Deshmukh, Rajendra M. Patrikar

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

Supply and Temperature Independent Voltage Reference Circuit in Subthreshold Region.

Vineysarathi Kokkula, Akash Joshi, Raghavendra B. Deshmukh

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

Real Time Mixing Index Measurement of Microchannels Using OpenCV.

Khuushi, Vanadana Jain, Rajendra M. Patrikar, Raghavendra B. Deshmukh

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

2017

Fast Architecture of Modular Inversion Using Itoh-Tsujii Algorithm.

Pravin Zode, Raghavendra B. Deshmukh, Abdus Samad

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2016

Design of resolution/power controllable Asynchronous Sigma-Delta Modulator.

Anita Arvind Deshmukh, Raghavendra B. Deshmukh

EURASIP J. Adv. Signal Process., 2016

Data dependent spurious power reduction for fixed width multiplier.

Bharti Navlani, Pankaj U. Joshi, Raghavendra B. Deshmukh

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015

Side channel attack resistant architecture for elliptic curve cryptography.

Pravin Zode, Raghavendra B. Deshmukh

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2013

Computational Functions' VLSI Implementation for Compressed Sensing.

Shrirang Korde, Amol Khandare, Raghavendra B. Deshmukh, Rajendra M. Patrikar

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

2011

Low Power Asynchronous Sigma-Delta Modulator Using Hysteresis Level Control.

Anita Arvind Deshmukh, Raghavendra B. Deshmukh, Rajendra M. Patrikar

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Design and Implementation of the Low Power 0.64mW, 380 KHz Continuous Time Sigma Delta ADC.

Aniruddha Kanhe, Bibhudendra Acharya, R. B. Deshmukh

Proceedings of the 4th International Conference on Emerging Trends in Engineering and Technology, 2011

2009

Design of Low Power Parallel Multiplier.

Rahul M. Badghare, Sanjiv Kumar Mangal, Raghavendra B. Deshmukh, Rajendra M. Patrikar

J. Low Power Electron., 2009

2007

FPGA Implementation of Low Power Parallel Multiplier.

Sanjiv Kumar Mangal, Raghavendra B. Deshmukh, Rahul M. Badghare, Rajendra M. Patrikar

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

Powering Wireless Sensor Nodes using Ambient RF Energy.

Shantanu A. Bhalerao, Abhishek V. Chaudhary, Raghavendra B. Deshmukh, Rajendra M. Patrikar

Proceedings of the IEEE International Conference on Systems, 2006