Raghava V. Cherabuddi

According to our database1, Raghava V. Cherabuddi authored at least 4 papers between 1994 and 1999.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

1999
Minimizing switchings of the function units through binding for low power.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1997
A low power based system partitioning and binding technique for multi-chip module architectures.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1996
A Graph-Based Approach to the Synthesis of Multi-Chip Module Architectures.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1994
Automated system partitioning for synthesis of multi-chip modules.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994


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