Rafael Trapani Possignolo

According to our database, Rafael Trapani Possignolo authored at least 17 papers between 2009 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

LiveHD: A Productive Live Hardware Development Flow.

Sheng-Hong Wang, Rafael Trapani Possignolo, Haven Blake Skinner, Jose Renau

IEEE Micro, 2020

LiveSim: A Fast Hot Reload Simulator for HDLs.

Haven Blake Skinner, Rafael Trapani Possignolo, Sheng-Hong Wang, Jose Renau

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

2019

EMI Architectural Model and Core Hopping.

Daphne I. Gorman, Rafael Trapani Possignolo, Jose Renau

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

SMatch: Structural Matching for Fast Resynthesis in FPGAs.

Rafael Trapani Possignolo, Jose Renau

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Improving the Productivity of Hardware Design.

Rafael Trapani Possignolo

PhD thesis, 2018

GPU NTC Process Variation Compensation With Voltage Stacking.

Rafael Trapani Possignolo, Elnaz Ebrahimi, Ehsan K. Ardestani, Alamelu Sankaranarayanan, José Luis Briz, Jose Renau

IEEE Trans. Very Large Scale Integr. Syst., 2018

Automated Pipeline Transformations with Fluid Pipelines.

Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau

Proceedings of the Advanced Logic Synthesis, 2018

2017

Liam: an actor based programming model for HDLs.

Haven Blake Skinner, Rafael Trapani Possignolo, Jose Renau

Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2017

Level shifter design for voltage stacking.

Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Managing Mismatches in Voltage Stacking with CoreUnfolding.

Ehsan K. Ardestani, Rafael Trapani Possignolo, José Luis Briz, Jose Renau

ACM Trans. Archit. Code Optim., 2016

SRAM voltage stacking.

Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Fluid Pipelines: Elastic circuitry meets Out-of-Order execution.

Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

LiveSynth: Towards an interactive synthesis flow.

Rafael Trapani Possignolo, Jose Renau

Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs.

Ilya Ganusov, Henri Fraisse, Aaron Ng, Rafael Trapani Possignolo, Sabya Das

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

Quantum-assisted QD-CFS signatures.

Rafael Trapani Possignolo, Cíntia Borges Margi, Paulo S. L. M. Barreto

J. Comput. Syst. Sci., 2015

2012

A Quantum-classical Hybrid Architecture for Security Algorithms Acceleration.

Rafael Trapani Possignolo, Cíntia B. Margi

Proceedings of the 11th IEEE International Conference on Trust, 2012

2009

Optimized joint NARX ANN - embedded processor design methodology.

Rafael Trapani Possignolo, Omar Hammami

Proceedings of the 16th IEEE International Conference on Electronics, 2009