Rafael Tornero

According to our database, Rafael Tornero authored at least 25 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Invited: Neuromorphic Vision Modalities in the NimbleAI 3D Chip.

Xabier Iturbe, Bernabé Linares-Barranco, Sio-Hoi Ieng, Arne Erdmann, Luca Peres, Oliver Rhodes, Rafael Tornero, Manolis Sifalakis, Marcel D. van de Burgwal, Amirreza Yousefzadeh, Maha Kooli, Riccardo Alidori, Pavel Zaykov

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

An Open-Source FPGA Platform for Shared-Memory Heterogeneous Many-Core Architecture Exploration.

Rafael Tornero, David Rodriguez, José Maria Martínez, José Flich

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms.

David Rodriguez, Rafael Tornero, José Flich

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips.

Xabier Iturbe, Nassim Abderrahmane, Jaume Abella, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Angélica Dávila, Arne Erdmann, Carles Estrada, Ander Fernández, Anna Fontanelli, José Flich, Gianluca Furano, Alejandro Hernán Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernández, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernabé Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Luján, Karel Masarík, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2021

Predictive Reliability and Fault Management in Exascale Systems: State of the Art and Perspectives.

Ramon Canal, Carles Hernández, Rafael Tornero, Alessandro Cilardo, Giuseppe Massari, Federico Reghenzani, William Fornaciari, Marina Zapater, David Atienza, Ariel Oleksiak, Wojciech Piatek, Jaume Abella

ACM Comput. Surv., 2021

From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience.

José Flich, Rafael Tornero, David Rodriguez, Davide Russo, José Maria Martínez, Carles Hernández

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

The RECIPE approach to challenges in deeply heterogeneous high performance systems.

Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, José Flich Cardo, Carles Hernández, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater

Microprocess. Microsystems, 2020

2019

Challenges in Deeply Heterogeneous High Performance Systems.

Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, José Flich, Carles Hernández, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018

Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems.

William Fornaciari, Giovanni Agosta, David Atienza, Carlo Brandolese, Leila Cammoun, Luca Cremona, Alessandro Cilardo, Albert Farrés, José Flich, Carles Hernández, Michal Kulchewski, Simone Libutti, José Maria Martínez, Giuseppe Massari, Ariel Oleksiak, Anna Pupykina, Federico Reghenzani, Rafael Tornero, Michele Zanella, Marina Zapater, Davide Zoni

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

2017

Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration.

José Flich, Alessandro Cilardo, Mario Kovaç, Rafael Tornero, Mirko Gagliardi, Edoardo Fusella, José Maria Martínez, Tomás Picornell

Proceedings of the Parallel Computing is Everywhere, 2017

MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems.

José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Gerald Guillaume, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Simone Libutti, Bruno Maitre, José Maria Martínez, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Tomás Picornell, Igor Piljic, Anna Pupykina, Federico Reghenzani, Isabelle Staub, Rafael Tornero, Marina Zapater, Davide Zoni

Proceedings of the Euromicro Conference on Digital System Design, 2017

2016

Enabling HPC for QoS-sensitive applications: The MANGO approach.

José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Alessandro Cilardo, William Fornaciari, Ynse Hoornenborg, Mario Kovac, Bruno Maitre, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Fabrice Roudet, Rafael Tornero, Davide Zoni

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Customizable Heterogeneous Acceleration for Tomorrow's High-Performance Computing.

Alessandro Cilardo, José Flich, Mirko Gagliardi, Rafael Tornero Gavilá

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2013

Acceleration of Communication-Aware Task Mapping Techniques through GPU Computing.

Javier Reyes, Juan M. Orduña, Guillermo Vigueras, Rafael Tornero

Proceedings of the 27th International Conference on Advanced Information Networking and Applications Workshops, 2013

2012

Designing Robust Routing Algorithms and Mapping Cores in Networks-on-Chip: A Multi-objective Evolutionary-based Approach.

Maurizio Palesi, Rafael Tornero, Juan Manuel Orduña, Vincenzo Catania, Daniela Panno

J. Univers. Comput. Sci., 2012

A Topology-Independent Mapping Technique for Application-Specific Networks-on-Chip.

Rafael Tornero, Maurizio Palesi, José Duato

Comput. Informatics, 2012

Computing Real-Time Dynamic Origin/Destination Matrices from Vehicle-to-Infrastructure Messages Using a Multi-Agent System.

Rafael Tornero, Javier Martínez, Joaquín Castelló

Proceedings of the Highlights on Practical Applications of Agents and Multi-Agent Systems, 2012

An Optimal Control Approach to Power Management for Multi-Voltage and Frequency Islands Multiprocessor Platforms under Highly Variable Workloads.

Paul Bogdan, Radu Marculescu, Siddharth Jain, Rafael Tornero Gavilá

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

A multi-agent system for obtaining dynamic origin/destination matrices on intelligent road networks.

Rafael Tornero, Javier Martínez, Joaquín Castelló

Proceedings of the Euro-American Conference on Telematics and Information Systems, 2012

2011

A Communication-Driven Routing Technique for Application-Specific NoCs.

Rafael Tornero, Juan Manuel Orduña, Andres Mejia, José Flich, José Duato

Int. J. Parallel Program., 2011

2010

Improving topological mapping on NoCs.

Rafael Tornero, Juan M. Orduña

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

2009

A multi-objective strategy for concurrent mapping and routing in networks on chip.

Rafael Tornero, Valentino Sterrantino, Maurizio Palesi, Juan M. Orduña

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Distance Constrained Mapping to Support NoC Platforms Based on Source Routing.

Rafael Tornero, Shashi Kumar, Saad Mubeen, Juan Manuel Orduña

Proceedings of the Euro-Par 2009, 2009

2008

A Communication-Aware Topological Mapping Technique for NoCs.

Rafael Tornero, Juan M. Orduña, Maurizio Palesi, José Duato

Proceedings of the Euro-Par 2008, 2008

CART: Communication-Aware Routing Technique for Application-Specific NoCs.

Rafael Tornero, Juan Manuel Orduña, Andres Mejia, José Flich, José Duato

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008