Rafael S. Ferreira

Affiliations:
  • Catholic University of Pelotas, Graduate Program on Electronic Engineering and Computing, Porto Alegre, Brazil


According to our database1, Rafael S. Ferreira authored at least 14 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A Hardware-Friendly Acceleration of VVC Affine Motion Estimation Using Decision Trees.
Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

A Hardware-Friendly Fast VVC Test Zone Search Algorithm Using Machine Learning.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

2023
Evaluation of Imprecise Subtractors into Test Zone Search for VVC Encoding.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

2022
The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures.
Circuits Syst. Signal Process., 2022

VVC Interpicture Prediction Using SAD with Imprecise Subtractors: A Quantitative Analysis.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2019
HEVC Interpolation Filter Architecture Using Hybrid Encoding Arithmetic Operators.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Approximate Subtractor Operator for Low-Power Video Coding Hardware Accelerators.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2017
A power-predictive environment for fast and power-aware ASIC-based FIR filter design.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Pruning and approximation of coefficients for power-efficient 2-D Discrete Tchebichef Transform.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Low power sum of absolute differences architecture using novel hybrid adder.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Physical implementation of an ASIC-oriented SRAM-based viterbi decoder.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017


  Loading...