Rafael A. Arce-Nazario

Orcid: 0000-0001-8036-6536

According to our database1, Rafael A. Arce-Nazario authored at least 19 papers between 2005 and 2024.

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Bibliography

2024
Analysis and computation of multidimensional linear complexity of periodic arrays.
Des. Codes Cryptogr., March, 2024

2023
Implementing an informal and culturally relevant computer science curriculum in a predominantly Hispanic-Spanish speaking community.
Proceedings of the Conference on Research in Equitable and Sustained Participation in Engineering, 2023

2021
On the cut number problem for the 4, and 5-cubes.
Discret. Appl. Math., 2021

2020
Multidimensional linear complexity analysis of periodic arrays.
Appl. Algebra Eng. Commun. Comput., 2020

2019
Bound for mixed exponential sums associated to binary good cyclic codes.
Finite Fields Their Appl., 2019

2018
New families of balanced symmetric functions and a generalization of Cusick, Li and Stǎnicǎ's conjecture.
Des. Codes Cryptogr., 2018

2017
On the covering radius of some binary cyclic codes.
Adv. Math. Commun., 2017

2016
Modules to Teach Parallel and Distributed Computing Using MPI for Python and Disco.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

2013
Algebraic Symmetries of Generic $(m+1)$-Dimensional Periodic Costas Arrays.
IEEE Trans. Inf. Theory, 2013

2012
Multidimensional Costas Arrays and Their Enumeration Using GPUs and FPGAs.
Int. J. Reconfigurable Comput., 2012

2011
Enumeration of Costas Arrays Using GPUs and FPGAs.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

2010
Reconfigurable Hardware Implementation of a Multivariate Polynomial Interpolation Algorithm.
Int. J. Reconfigurable Comput., 2010

2009
A Systolic Array Based Architecture for Implementing Multivariate Polynomial Interpolation Tasks.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

2008
Mapping of Discrete Cosine Transforms onto Distributed Hardware Architectures.
J. Signal Process. Syst., 2008

Architectural Model and Resource Estimation for Distributed Hardware Implementation of Discrete Signal Transforms.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

2007
Algorithmic-level exploration of discrete signal transforms for partitioning to distributed hardware architectures.
IET Comput. Digit. Tech., 2007

2006
High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA Architectures.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Effects of High-Level Discrete Signal Transform Formulations on Partitioning for Multi-FPGA Architectures.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2005
A diagnostic method for detecting and assessing the impact of physical design optimizations on routing.
Proceedings of the 2005 International Symposium on Physical Design, 2005


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