Radu Teodorescu

Orcid: 0000-0002-6474-2201

According to our database1, Radu Teodorescu authored at least 50 papers between 2001 and 2024.

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Bibliography

2024
Voltage Noise-Based Adversarial Attacks on Machine Learning Inference in Multi-Tenant FPGA Accelerators.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

2023
TEESec: Pre-Silicon Vulnerability Discovery for Trusted Execution Environments.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2022
Special Issue on Top Picks From the 2021 Computer Architecture Conferences.
IEEE Micro, 2022

DNNShield: Dynamic Randomized Model Sparsification, A Defense Against Adversarial Machine Learning.
CoRR, 2022

A Pre-Silicon Approach to Discovering Microarchitectural Vulnerabilities in Security Critical Applications.
IEEE Comput. Archit. Lett., 2022

A Systematic Look at Ciphertext Side Channels on AMD SEV-SNP.
Proceedings of the 43rd IEEE Symposium on Security and Privacy, 2022

ENCLYZER: Automated Analysis of Transient Data Leaks on Intel SGX.
Proceedings of the 2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED), 2022

Characterizing Side-Channel Leakage of DNN Classifiers though Performance Counters.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

2021
HASI: Hardware-Accelerated Stochastic Inference, A Defense Against Adversarial Machine Learning Attacks.
CoRR, 2021

INTROSPECTRE: A Pre-Silicon Framework for Discovery and Analysis of Transient Execution Vulnerabilities.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Using Undervolting as an on-Device Defense Against Adversarial Machine Learning Attacks.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

A Fused Inference Design for Pattern-Based Sparse CNN on Edge Devices.
Proceedings of the 28th IEEE International Conference on High Performance Computing, 2021

Fused DSConv: Optimizing Sparse CNN Inference for Execution on Edge Devices.
Proceedings of the 21st IEEE/ACM International Symposium on Cluster, 2021

2020
RNNFast: An Accelerator for Recurrent Neural Networks Using Domain-Wall Memory.
ACM J. Emerg. Technol. Comput. Syst., 2020

SPEECHMINER: A Framework for Investigating and Measuring Speculative Execution Vulnerabilities.
Proceedings of the 27th Annual Network and Distributed System Security Symposium, 2020

A Pattern-Based API for Mapping Applications to a Hierarchy of Multi-Core Devices.
Proceedings of the 20th IEEE/ACM International Symposium on Cluster, 2020

2019
Isolating Speculative Data to Prevent Transient Execution Attacks.
IEEE Comput. Archit. Lett., 2019

Distributing Deep Neural Networks with Containerized Partitions at the Edge.
Proceedings of the 2nd USENIX Workshop on Hot Topics in Edge Computing, 2019

Accident Risk Prediction based on Heterogeneous Sparse Data: New Dataset and Insights.
Proceedings of the 27th ACM SIGSPATIAL International Conference on Advances in Geographic Information Systems, 2019

Adaptive parallel execution of deep neural networks on heterogeneous edge devices.
Proceedings of the 4th ACM/IEEE Symposium on Edge Computing, 2019

SpecShield: Shielding Speculative Data from Microarchitectural Covert Channels.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
C-Graph: A Highly Efficient Concurrent Graph Reachability Query Framework.
Proceedings of the 47th International Conference on Parallel Processing, 2018

NVCool: When Non-Volatile Caches Meet Cold Boot Attacks.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

2017
Respin: Rethinking Near-Threshold Multiprocessor Design with Non-volatile Memory.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

2016
One Bit Flips, One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation.
Proceedings of the 25th USENIX Security Symposium, 2016

Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

Core tunneling: Variation-aware voltage noise mitigation in GPUs.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
Commentary: When the brain takes a break: a model-based analysis of mind wandering.
Frontiers Comput. Neurosci., 2015

Authenticache: harnessing cache ECC for system authentication.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

2014
On Using the Roofline Model with Lower Bounds on Data Movement.
ACM Trans. Archit. Code Optim., 2014

Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

NVSleep: Using non-volatile memory to enable fast sleep/wakeup of idle cores.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Using STT-RAM to enable energy-efficient near-threshold chip multiprocessors.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
Runtime failure rate targeting for energy-efficient reliability in chip microprocessors.
Concurr. Comput. Pract. Exp., 2013

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012
Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units.
IEEE Comput. Archit. Lett., 2012

VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011
StVEC: A Vector Instruction Extension for High Performance Stencil Computation.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Flexible Error Protection for Energy Efficient Reliable Architectures.
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010

Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

2008
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

HARD: Hardware-Assisted Lockset-based Race Detection.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

2006
SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback.
IEEE Micro, 2006

Log-based architectures for general-purpose monitoring of deployed code.
Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, 2006

2005
Prototyping Architectural Support for Program Rollback Using FPGAs.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

2004
Using code collection to support large applications on mobile devices.
Proceedings of the 10th Annual International Conference on Mobile Computing and Networking, 2004

2001
Using JIT Compilation and Configurable Runtime Systems for Efficient Deployment of Java Programs on Ubiquitous Devices.
Proceedings of the Ubicomp 2001: Ubiquitous Computing, 2001


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