Rachid Rayess

According to our database, Rachid Rayess authored at least 6 papers between 2002 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

A Fully Integrated 1 GHz 8A I_max Step-Down and Step-Up Switched Capacitor Voltage Regulator in 3 nm FinFET Technology Featuring Auto Mode Transition.

Arvind Raghavan, Keng Chen, Huanhuan Zhang, Sivaraman Masilamani, Tamir Salus, Rachid Rayess, Gayathri Devi Sridharan, Aruna Payala, Jianrong Chen

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2024

2022

A IMax |_max^, Fully Integrated Multi-Phase Voltage Regulator with 91.5% Peak Efficiency at 1.8 to 1V, Operating at 50MHz and Featuring a Digitally Assisted Controller with Automatic Phase Shedding and Soft Switching in 4nm Class FinFET CMOS.

Christopher Schaef, Tamir Salus, Rachid Rayess, Siddarth Kulasekaran, Mat Manusharow, Kaladhar Radhakrishnan, Jonathan Douglas

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2015

Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures.

Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer

ACM Trans. Comput. Syst., 2015

2014

Efficient Spatial Processing Element Control via Triggered Instructions.

Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer

IEEE Micro, 2014

2013

Triggered instructions: a control paradigm for spatially-programmed architectures.

Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2002

Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU.

Joel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah, Emily Shriver, Shi-Huang Yin, Shannon V. Morton

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002