Rached Tourki

According to our database1, Rached Tourki authored at least 80 papers between 1998 and 2019.

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Bibliography

2019
Low latency multicasting architecture implemented using new network topology.
Microprocess. Microsystems, 2019

2018
Performance Analysis of a Multicore Based LEON3 Integrating a RTOS.
Proceedings of the 15th International Multi-Conference on Systems, Signals & Devices, 2018

2017
High-Level Implementation of a Chaotic and AES Based Crypto-System.
J. Circuits Syst. Comput., 2017

Lightweight Encryption Algorithm Based on Modified XTEA for Low-Resource Embedded Devices.
Proceedings of the 21st International Database Engineering & Applications Symposium, 2017

HLS design of a hardware accelerator for Homomorphic Encryption.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016
An efficient hardware implementation of parallel EBCOT algorithm for JPEG 2000.
J. Real Time Image Process., 2016

A deep analysis of SEU consequences in the internal memory of LEON3 processor.
Proceedings of the 17th Latin-American Test Symposium, 2016

Simulation-based verification of large-integer arithmetic circuits.
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

Stepwise SystemC/TLM-2 models structuring and optimizations.
Proceedings of the 11th International Design & Test Symposium, 2016

A flexible RNS-based large polynomial multiplier for Fully Homomorphic Encryption.
Proceedings of the 11th International Design & Test Symposium, 2016

On Elliptic Curve Cryptography implementations and evaluation.
Proceedings of the 2nd International Conference on Advanced Technologies for Signal and Image Processing, 2016

Performance evaluation and design considerations of lightweight block cipher for low-cost embedded devices.
Proceedings of the 13th IEEE/ACS International Conference of Computer Systems and Applications, 2016

A Selective Encryption Scheme with Multiple Security Levels for the H.264/AVC Video Coding Standard.
Proceedings of the 2016 IEEE International Conference on Computer and Information Technology, 2016

Efficient Hybrid Encryption System Based on Block Cipher and Chaos Generator.
Proceedings of the 2016 IEEE International Conference on Computer and Information Technology, 2016

2015
Impact of retinal vascular tortuosity on retinal circulation.
Neural Comput. Appl., 2015

An AOP-Based Fault Injection Environment for Cryptographic SystemC Designs.
J. Circuits Syst. Comput., 2015

Enhancing a 32-Bit Processor Core with Efficient Cryptographic Instructions.
J. Circuits Syst. Comput., 2015

Computational analysis of blood flow in the retinal arteries and veins using fundus image.
Comput. Math. Appl., 2015

A new approach for encryption system based on block cipher algorithms and logistic function.
Proceedings of the 12th IEEE International Multi-Conference on Systems, Signals & Devices, 2015

2014
Efficient implementation of Sobel edge detection algorithm on CPU, GPU and FPGA.
Int. J. Adv. Media Commun., 2014

A low-resource 32-bit datapath ECDSA design for embedded applications.
Proceedings of the International Carnahan Conference on Security Technology, 2014

Instruction set extensions of AES algorithms for 32-bit processors.
Proceedings of the International Carnahan Conference on Security Technology, 2014

MatLab acceleration for DWT "Daubechies 9/7" for JPEG2000 standard on GPU.
Proceedings of the Global Summit on Computer & Information Technology, 2014

Parallel implementation of the discrete wavelet transform on graphics processing units.
Proceedings of the 2014 1st International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), 2014

2013
Effects of a magnetic field environment on quantum cloning of qubits.
Quantum Inf. Process., 2013

Optimized spatio-temporal descriptors for real-time fall detection: comparison of support vector machine and Adaboost-based classification.
J. Electronic Imaging, 2013

A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme.
Integr., 2013

High-level implementation of Video compression chain coding based on MCTF lifting scheme.
Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013

Preliminary study of block matching algorithms for wavelet-based t+2D video coding.
Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013

Blood vessels extraction and classification into arteries and veins in retinal images.
Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013

An FPGA implementation of the SHA-3: The BLAKE hash function.
Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013

Integral image computation on GPU.
Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013

VCRBCM: A low latency virtual channel router architecture based on blocking controller manger.
Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013

A modular and generic router TLM model for speedup network-on-chip topology generation.
Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013

Automatic estimation of the noise model in fundus images.
Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013

2012
Monitoring transaction level SystemC models using a generic and aspect-oriented framework.
Int. J. Comput. Aided Eng. Technol., 2012

System level modeling methodology of NoC design from UML-MARTE to VHDL.
Des. Autom. Embed. Syst., 2012

Data traffic load balancing and QoS in IEEE 802.11 network: Experimental study of the signal strength effect.
Comput. Electr. Eng., 2012

Definition and Performance Evaluation of a Robust SVM Based Fall Detection Solution.
Proceedings of the Eighth International Conference on Signal Image Technology and Internet Based Systems, 2012

Implementation of CPA analysis against AES design on FPGA.
Proceedings of the International Conference on Communications and Information Technology, 2012

A mesochronous outfit for Network-on-Chip's interconnects retiming.
Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

Performances of the AES design in 0.18μm CMOS technology.
Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

A compact 32-bit AES design for embedded system.
Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

Hardware Implementation of a Configurable Motion Estimator for Adjusting the Video Coding Performances.
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2012

2011
A high-speed four-phase clock generator for low-power on-chip SerDes applications.
Microelectron. J., 2011

Wireless propagation channel modeling for optimized Handoff algorithms in wireless LANs.
Comput. Electr. Eng., 2011

FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

2010
Design and Hardware Implementation of QoSS - AES Processor for Multimedia applications.
Trans. Data Priv., 2010

A flexible Image Processing Design based on 2D DCT/IDCT for a System on a Programmable Chip.
Int. J. Comput., 2010

Performance evaluation of MIC@R NoC for real-time applications.
Int. J. Comput. Aided Eng. Technol., 2010

A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantization.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2010

Design and implementation of low latency network interface for network on chip.
Proceedings of the 5th International Design and Test Workshop, 2010

2009
Automated Breast Cancer Diagnosis Based on GVF-Snake Segmentation, Wavelet Features Extraction and Fuzzy Classification.
J. Signal Process. Syst., 2009

Nouvelles architectures génériques de NoC.
Tech. Sci. Informatiques, 2009

Design of Reconfigurable Image Encryption Processor Using 2-D Cellular Automata Generator.
Int. J. Comput. Sci. Appl., 2009

Efficient hardware architecture of 2D-scan-based wavelet watermarking for image and video.
Comput. Stand. Interfaces, 2009

Experimental Performances Analysis of Load Balancing Algorithms in IEEE 802.11
CoRR, 2009

2008
Arbiter synthesis approach for SoC multi-processor systems.
Comput. Electr. Eng., 2008

2007
System on Chips optimization using ABV and automatic generation of SystemC codes.
Microprocess. Microsystems, 2007

Rapid Prototyping IP for Autocorrelation Computation.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

MIC@R : A Generic Low Latency Router for On-Chip Networks.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

A Reconfigurable Implementation of the New Secure Hash Algorithm.
Proceedings of the The Second International Conference on Availability, 2007

2006
G729 Voice Decoder Design.
J. VLSI Signal Process., 2006

2005
A novel formal verification approach for RTL hardware IP cores.
Comput. Stand. Interfaces, 2005

An automatic ABV methodology enabling PSL assertions across SLD flow for SOCs modeled in SystemC.
Comput. Electr. Eng., 2005

Classification of tissues by neural network.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004
High performance architecture of integrated protocols for encoded video application.
Comput. Stand. Interfaces, 2004

Co-simulation and communication synthesis approach for intellectual properties based SoCs.
Comput. Electr. Eng., 2004

2002
Problems in pattern classification in high dimensional spaces: behavior of a class of combined neuro-fuzzy classifiers.
Fuzzy Sets Syst., 2002

2001
TCP flow control technique for an interworking interface: hardware implementation.
Comput. Stand. Interfaces, 2001

A Flow Control Approach for Encoded Video Applications Over ATM Network.
Proceedings of the Sixth IEEE Symposium on Computers and Communications (ISCC 2001), 2001

2000
Design of New Optimized Architecture Processor for DWT.
Real Time Imaging, 2000

Rapid prototyping of an ATM programmable associative operator.
J. Syst. Archit., 2000

VLSI design of 1-D DWT architecture with parallel filters.
Integr., 2000

Effect of the Feature Vector Size on the Generalization Error: The Case of MLPNN and RBFNN Classifiers.
Proceedings of the 15th International Conference on Pattern Recognition, 2000

A nonlinear acoustic echo canceller for hands-free telephony.
Proceedings of the 10th European Signal Processing Conference, 2000

1999
A Speaker Independent Arabic Isolated Spoken Digits Recognition System Using Fuzzy Kohonen Clustering Network.
Proceedings of the International Conference on Artificial Neural Nets and Genetic Algorithms, 1999

1998
An arbiter synthesis approach based on arbitration scheme generation/selection for HW/SW co-design.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Implementation of an acoustic echo canceller based on NLMS-neural networks structures by using the VHDL.
Proceedings of the 1998 IEEE International Conference on Communications, 1998

Rapid Prototyping of Multi-Recommendation Modem (Abstract).
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998


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